Microchip Technology AT24C04D-SSHM-T

Overview

AT24C04D-SSHM-T from Microchip Technology (formerly Atmel) is a 4-Kbit I²C-compatible serial EEPROM organized as 512 × 8 bits, operating from 1.7V to 3.6V, supporting Standard (100 kHz), Fast (400 kHz), and Fast Mode Plus (1 MHz at ≥2.5V) I²C speeds, with hardware write protection via WP pin, and used for nonvolatile parameter storage in embedded control systems.

For engineers reviewing the AT24C04D-SSHM-T datasheet, AT24C04D-SSHM-T pinout, AT24C04D-SSHM-T application, or AT24C04D-SSHM-T equivalent, this page delivers verified package mapping (8-lead SOIC), confirmed I²C timing modes, validated page-write behavior (16-byte boundary), real-world noise suppression features (Schmitt triggers + input filtering), and precise device addressing logic (A1/A2 pins, 7-bit slave address format).

Technical Context

The AT24C04D-SSHM-T operates exclusively as an I²C slave device with fixed 7-bit device type identifier '1010' (0xA), where A1 and A2 pins determine bits 3–2 of the slave address-enabling up to four devices on one bus. Its internal 9-bit word address space maps to 512 bytes across 32 pages of 16 bytes each, with automatic address rollover during sequential reads.

Write operations are self-timed (≤5 ms max), support byte and page writes (with partial-page capability), and require explicit Stop condition initiation; Acknowledge Polling enables deterministic completion detection. The WP pin samples state at Stop condition edge with defined tSU.WP/tHD.WP timing, and floating A1/A2 pins are internally pulled down to GND.

Key Specifications

Pinout & Package

AT24C04D-SSHM-T is packaged in an 8-lead SOIC (Small Outline Integrated Circuit) with standard 1.27 mm pitch, RoHS-compliant lead-free finish, and moisture sensitivity level (MSL) 1 - suitable for reflow soldering without baking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT24C04C-SSHM-T, the AT24C04D-SSHM-T enables faster configuration loading in 1.7V systems and broader low-voltage compatibility; versus CAT24C04WI-GT3, it provides standardized WP polarity and consistent 100-year retention spec across temperature, simplifying qualification for medical and industrial use.

Availability

AT24C04D-SSHM-T is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, and automotive body control modules requiring stable component supply, long-lifecycle support, and guaranteed RoHS-compliant sourcing.

Supply support for AT24C04D-SSHM-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and maintains full product continuity, quality control, and technical documentation for the AT24C04D-SSHM-T family.

The AT24C04D belongs to Microchip's serial EEPROM product line, designed specifically for reliable, low-power nonvolatile storage in space- and power-constrained embedded systems across industrial, medical, and automotive markets.

FAQ

What is the maximum I²C clock frequency supported by the AT24C04D-SSHM-T?

The AT24C04D-SSHM-T supports three I²C speed modes: 100 kHz (Standard Mode), 400 kHz (Fast Mode), and 1 MHz (Fast Mode Plus). The 1 MHz mode requires VCC ≥2.5V; below that, maximum speed is 400 kHz. All modes operate across the full 1.7V–3.6V supply range, making AT24C04D-SSHM-T suitable for both 1.8V and 3.3V host systems without voltage translation.

How does the WP pin function on the AT24C04D-SSHM-T?

The WP (Write Protect) pin on the AT24C04D-SSHM-T is an active-high input that disables all write operations-including byte, page, and erase-when driven to VCC (or valid VIH). When tied to GND or left floating, writes are enabled. The pin state is sampled at the Stop condition edge, with defined setup (tSU.WP) and hold (tHD.WP) timing requirements. This hardware-level protection ensures AT24C04D-SSHM-T data integrity even during firmware crashes or brown-out conditions.

Can the AT24C04D-SSHM-T be used with multiple devices on the same I²C bus?

Yes, the AT24C04D-SSHM-T supports up to four devices on a single I²C bus using its A1 and A2 hardware address pins. These pins configure bits 3 and 2 of the 7-bit slave address (base 0x50), yielding addresses 0x50–0x53. Internally pulled down when floating, A1/A2 allow flexible addressing via simple VCC/GND connections - enabling scalable parameter storage across distributed nodes without software address management overhead in the AT24C04D-SSHM-T implementation.

What is the page size and write timing behavior of the AT24C04D-SSHM-T?

The AT24C04D-SSHM-T has a 16-byte page size (32 pages × 16 bytes = 512 bytes). Page writes complete within 5 ms maximum, and partial-page writes (e.g., 3 or 12 bytes) are fully supported. During a page write, the internal address counter increments automatically; crossing the 16-byte boundary causes rollover to the start of the same page - a behavior that must be avoided in firmware to prevent unintended overwrites. This page architecture makes AT24C04D-SSHM-T ideal for efficient bulk configuration updates.

Is the AT24C04D-SSHM-T compatible with standard I²C protocol requirements?

Yes, the AT24C04D-SSHM-T fully complies with standard I²C specifications: it uses open-drain SDA/SCL with Schmitt-trigger inputs and spike filtering, requires external pull-ups (≤10 kΩ), recognizes Start/Stop conditions, implements ACK/NACK handshaking on the 9th clock cycle, and maintains data stability during SCL high periods. Its timing parameters (tLOW, tHIGH, tSU:STA, etc.) meet I²C Standard/Fast/FM+ specs - ensuring interoperability with any compliant master, including ARM Cortex-M, PIC, and ESP32 controllers in AT24C04D-SSHM-T deployments.