Microchip Technology AT24C1024BN-SH25-T
- Part No.:
- AT24C1024BN-SH25-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT24C1024BN-SH25-T.pdf
- Description:
- IC EEPROM 1MBIT I2C 1MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT24C1024BN-SH25-T from Microchip Technology (formerly Atmel) is a 1 Mbit (131,072 × 8) two-wire serial EEPROM with 2.5V operation (2.5V to 5.5V), 1 MHz clock rate at 5V/2.5V, hardware write protection via WP pin, and 256-byte page write capability. It serves as nonvolatile configuration storage in industrial controllers, power supply monitors, and embedded telemetry modules.
For engineers reviewing the AT24C1024BN-SH25-T datasheet, AT24C1024BN-SH25-T pinout, AT24C1024BN-SH25-T application, or AT24C1024BN-SH25-T equivalent, key selection criteria include voltage range compatibility (2.5V–5.5V), I²C bus timing at 1 MHz, page write endurance (1M cycles), data retention (40 years), and JEDEC SOIC-8 package footprint.
Technical Context
The AT24C1024BN-SH25-T implements a standard two-wire (I²C-compatible) interface with Schmitt-triggered, noise-filtered SDA/SCL inputs and bidirectional open-drain data transfer. Its internal address space is segmented into 512 pages of 256 bytes each, requiring 17-bit addressing with P0 bit embedded in the device address byte.
Device addressing uses A1/A2 pins to support up to four devices on a shared bus; both pins are internally pulled down when floating but must be hardwired for deterministic multi-device configurations. Write protection is enforced by tying WP high to VCC, disabling all write operations including page and byte writes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1,048,576 bits (131,072 × 8), organized as 512 pages × 256 bytes - enables full firmware parameter sets or calibration tables in compact systems. |
| Supply Voltage Range | 2.5V to 5.5V - supports direct interfacing with 3.3V and 5V microcontrollers without level-shifting. |
| Max Clock Frequency | 1 MHz at 2.5V/5V - doubles write throughput vs. 400 kHz variants, critical for high-frequency logging applications. |
| Page Write Capacity | 256-byte page writes - reduces I²C transaction overhead by 99% compared to single-byte writes for bulk updates. |
| Write Endurance | 1,000,000 cycles per page - ensures >10 years of daily 274-write cycles in field-deployed industrial sensors. |
| Data Retention | 40 years at +85°C - guarantees long-term reliability in unattended infrastructure monitoring equipment. |
| Standby Current | 2.0 µA at 2.5V - minimizes quiescent power in battery-backed real-time clocks and energy-harvesting nodes. |
Pinout & Package
AT24C1024BN-SH25-T is packaged in an 8-lead JEDEC SOIC (8S1), 3.9 mm × 4.9 mm body, 1.27 mm lead pitch, NiPdAu lead finish. Pin 1 is marked with a dot; leads are gull-wing profile with 0.31–0.51 mm width.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| NC | No Connect | Unbonded die pad - must remain unconnected; no pull-up/down required. |
| A1 | Device Address Input | LSB of hardware address; tied high/low or left floating (internally pulled down) to select one of four possible bus addresses. |
| A2 | Device Address Input | MSB of hardware address; used with A1 to configure unique I²C slave address among up to four devices. |
| GND | Ground Reference | Primary return path for VCC and I/O; requires low-impedance connection to system ground plane. |
| VCC | Power Supply | 2.5V–5.5V input; bypass capacitor (0.1 µF ceramic) required within 5 mm of pin for noise immunity. |
| WP | Write Protect Control | Active-high hardware lock; tied to VCC disables all writes, including software-initiated page/byte operations. |
| SCL | Serial Clock Input | Positive-edge sampled clock; requires external pull-up (1.3 kΩ @ 2.5V) and meets tLOW/tHIGH timing per AC specs. |
| SDA | Serial Data I/O | Open-drain bidirectional bus line; shares pull-up with SCL and other I²C devices on same segment. |
Key Features
| Feature | Design Value |
|---|---|
| Two-wire Serial Interface | Fully compatible with I²C protocol (standard-mode), enabling seamless integration with ARM Cortex-M, PIC, and ESP32 host controllers. |
| 256-byte Page Write Mode | Reduces firmware update time by 256× versus byte writes - critical for OTA configuration rollouts in edge gateways. |
| Schmitt Trigger Inputs | Rejects <100 ns noise spikes on SDA/SCL, eliminating false start/stop detection in electrically noisy motor drive environments. |
| Self-timed Write Cycle | 5 ms typical internal erase/write completion - allows host MCU to poll ACK instead of fixed delays, improving real-time scheduling. |
| Hardware + Software Write Protection | WP pin + internal software lock enable dual-layer security for critical calibration or licensing data in medical devices. |
Applications
| Industrial PLC Configuration Storage | Smart Energy Meter Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation lines. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via I²C during boot and runtime reconfiguration. Use Value: Enables field-upgradable control logic without firmware reflashing; 40-year retention ensures parameter integrity across equipment lifecycle. | Use Scenario: Holding metrology calibration coefficients, tariff tables, and tamper-event logs in ANSI C12.20-compliant electricity meters. IC Role / Device Role / Timing Role: Secure, write-protected memory for legally binding measurement data with hardware-enforced WP pin lockdown. Use Value: Meets ANSI/IEEE accuracy traceability requirements; 1M write cycles support daily recalibration over 27 years. |
| Telecom Power Supply Monitoring | Medical Infusion Pump Safety Parameters |
Use Scenario: Recording thermal derating curves, fault history, and firmware version stamps in -48V DC telecom rectifiers operating at +85°C ambient. IC Role / Device Role / Timing Role: High-temp EEPROM for black-box event logging with guaranteed 40-year data retention at extended temperature. Use Value: Supports Telcordia GR-1089-CORE ESD/EMI compliance; low 2.0 µA standby current extends backup battery life. | Use Scenario: Storing drug library limits, dose safety interlocks, and audit trail timestamps in FDA Class II infusion pumps. IC Role / Device Role / Timing Role: Fail-safe nonvolatile memory with hardware write protect to prevent unauthorized parameter modification. Use Value: Enables IEC 62304 SW validation; WP pin hardwired to VCC satisfies ISO 14971 risk control for critical safety data. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C1024D-SSHM-T | Same 1 Mbit density and SOIC-8 package, but rated for 1.7V–5.5V operation and features enhanced ESD robustness (4 kV HBM). | Preferred for portable medical devices requiring ultra-low-voltage wake-up or high-noise hospital environments. | Select when wider voltage margin or higher ESD immunity is mandatory; not drop-in due to different VCC min spec. |
| BR24G1ME2SPIJ-3GE2 | 1 Mbit SPI interface (not I²C), 1.7V–5.5V, 10 MHz clock, 256-byte page size, same 1M write endurance. | Suitable where host MCU lacks I²C hardware or requires faster sequential reads than I²C permits. | Choose only if SPI bus is available and timing-critical logging demands >1 MHz throughput; requires PCB layout change. |
Compared with AT24C1024D-SSHM-T, the AT24C1024BN-SH25-T offers tighter 2.5V–5.5V regulation for stable 3.3V systems but lacks sub-2.5V operation; versus BR24G1ME2SPIJ-3GE2, it retains I²C compatibility for legacy designs but trades off peak speed for bus simplicity and pin count reduction.
Availability
AT24C1024BN-SH25-T is available at Aetrix Electronics and suitable for industrial PLCs, smart energy meters, telecom power supplies, and medical infusion pumps requiring stable component supply and long-lifecycle assurance.
Supply support for AT24C1024BN-SH25-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with emphasis on industrial, automotive, and aerospace reliability standards.
The AT24C1024BN-SH25-T belongs to Microchip's AT24Cxx serial EEPROM family, engineered for robust nonvolatile data storage in harsh environments where power loss resilience, long-term data integrity, and I²C bus compatibility are essential.
FAQ
What is the maximum I²C clock frequency supported by the AT24C1024BN-SH25-T?
The AT24C1024BN-SH25-T supports up to 1 MHz clock frequency when operated at 2.5V or 5V supply, as specified in Table 3-3 of the datasheet. This is distinct from the 400 kHz limit applicable to 1.8V operation. The 1 MHz capability enables faster bulk writes and reduces configuration load time in time-sensitive applications like power supply sequencing.
Does the AT24C1024BN-SH25-T require external pull-up resistors on SDA and SCL lines?
Yes, the AT24C1024BN-SH25-T requires external pull-up resistors on both SDA and SCL lines because its I/O pins are open-drain. For 2.5V operation, a 1.3 kΩ resistor is recommended per the AC test conditions in the datasheet. Proper pull-up values ensure signal rise times meet tR ≤ 300 ns and maintain bus integrity across multiple devices.
How does the WP pin function on the AT24C1024BN-SH25-T?
The WP (Write Protect) pin on the AT24C1024BN-SH25-T is an active-high hardware lock. When tied to VCC, it inhibits all write operations-including byte, page, and software write commands-while allowing unrestricted reads. If left floating, it is internally pulled down, enabling normal writes; however, Microchip recommends hardwiring WP to GND or VCC for deterministic behavior in production systems.
What package type is used for the AT24C1024BN-SH25-T?
The AT24C1024BN-SH25-T uses an 8-lead JEDEC SOIC package (designated 8S1 in ordering codes), with 0.150" body width, gull-wing leads, and NiPdAu lead finish. Its dimensions are 4.9 mm × 3.9 mm × 1.75 mm max height, compliant with MS-012 variation AA, making it compatible with standard SOIC-8 footprints and reflow profiles.
Can multiple AT24C1024BN-SH25-T devices share the same I²C bus?
Yes, up to four AT24C1024BN-SH25-T devices can share a single I²C bus using hardware address differentiation via the A1 and A2 pins. Each device's 7-bit slave address incorporates these two bits, allowing unique addressing (e.g., 0x50–0x53). All devices must use identical VCC and timing settings, and total bus capacitance must remain ≤400 pF to maintain 1 MHz operation.
AT24C1024BN-SH25-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 550 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT24C1024BN-SH25-T FAQ
1.How can I place an order for AT24C1024BN-SH25-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C1024BN-SH25-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C1024BN-SH25-T reliable?
The price and inventory of AT24C1024BN-SH25-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C1024BN-SH25-T is usually 5 days.
3.What payment methods are accepted for AT24C1024BN-SH25-T?
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4.How is shipping managed for AT24C1024BN-SH25-T?
AT24C1024BN-SH25-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C1024BN-SH25-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C1024BN-SH25-T?
For technical support, including AT24C1024BN-SH25-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C1024BN-SH25-T requirements.
6.How does Aetrix verify that AT24C1024BN-SH25-T is sourced from the original manufacturer or authorized distributors?
All AT24C1024BN-SH25-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C1024BN-SH25-T meets industry standards.
7.What is the process for return or replacement of AT24C1024BN-SH25-T?
All AT24C1024BN-SH25-T units undergo pre-shipment inspection (PSI). If there is an issue with AT24C1024BN-SH25-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C1024BN-SH25-T part is unused and in its original packaging.
Return procedure for AT24C1024BN-SH25-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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