Microchip Technology AT24C1024B-PU25
- Part No.:
- AT24C1024B-PU25
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT24C1024B-PU25.pdf
- Description:
- IC EEPROM 1MBIT I2C 1MHZ 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,073
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Product details
Overview
AT24C1024B-PU25 from Microchip Technology (formerly Atmel) is a 1 Mbit (131,072 × 8) two-wire serial EEPROM optimized for low-voltage industrial and commercial systems. It operates from 2.5V to 5.5V, supports 1 MHz clock rate at 2.5V/5V, features hardware write protection via WP pin, and delivers 1,000,000 write cycles per page with 40-year data retention. It is used in embedded controllers for configuration storage, calibration data logging, and firmware parameter backup.
For engineers reviewing the AT24C1024B-PU25 datasheet, AT24C1024B-PU25 pinout, AT24C1024B-PU25 application, or AT24C1024B-PU25 equivalent, key selection criteria include voltage range compatibility (2.5V–5.5V), 256-byte page write capability, cascading support for up to four devices on one bus, and PDIP-8 packaging with through-hole mounting for prototyping and legacy board designs.
Technical Context
The AT24C1024B-PU25 implements a standard I²C-compatible two-wire interface with open-drain SDA and edge-triggered SCL, supporting both random and sequential read modes plus byte/page write operations. Its internal address space is segmented into 512 pages of 256 bytes each, requiring a 17-bit word address where the most significant bit (P0) is embedded in the device address byte.
Device addressing uses A1 and A2 pins to select among up to four devices on the same bus; when left unconnected, they are internally pulled low. The WP pin enables hardware-level write inhibition when tied to VCC, while Schmitt-triggered inputs and noise-filtered logic ensure robust operation in electrically noisy environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1,048,576 bits (131,072 × 8), organized as 512 pages × 256 bytes - enables full system configuration storage without external memory expansion |
| Supply Voltage Range | 2.5V to 5.5V - compatible with 3.3V and 5V logic systems, eliminating need for level-shifting in mixed-voltage designs |
| Max Clock Frequency | 1 MHz at 2.5V/5V - supports high-speed parameter updates in real-time control applications |
| Write Cycle Time | 5 ms typical - defines minimum interval between successive write commands; impacts firmware update latency |
| Endurance | 1,000,000 write cycles per page - ensures reliable operation over 10+ years in daily calibration logging use cases |
| Data Retention | 40 years at +85°C - guarantees long-term integrity of stored calibration coefficients and security keys |
| Interface Protocol | Standard two-wire (I²C) serial interface with ACK/NACK handshake - interoperable with all I²C masters including ARM Cortex-M, PIC, and ESP32 microcontrollers |
Pinout & Package
AT24C1024B-PU25 is supplied in an 8-lead PDIP (Plastic Dual In-line Package), 0.300" wide body, suitable for through-hole prototyping and industrial control PCBs. Pin 1 is marked by a notch or dot at the top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| NC | No Connect | Unused pin; must remain unconnected to avoid unintended coupling or ESD paths |
| A1 | Device Address Input | Hardware-selectable LSB of device address; hardwire to VCC/GND or leave floating (internally pulled low) to configure one of four possible bus addresses |
| A2 | Device Address Input | Hardware-selectable MSB of device address; used with A1 to enable up to four AT24C1024B-PU25 devices on a shared I²C bus |
| GND | Ground Reference | System return path for all internal circuitry; requires low-impedance connection to minimize noise-induced read errors |
| VCC | Power Supply | Primary supply input (2.5V–5.5V); decoupling capacitor (0.1 µF ceramic) required within 10 mm for stable I²C timing |
| WP | Write Protect Control | Active-high hardware lock: tie to VCC to disable all writes; tie to GND for normal operation; floating defaults to write-enabled |
| SCL | Serial Clock Input | Master-generated clock signal; rising edge latches address/data bits; requires external pull-up resistor (typically 2.2–10 kΩ) |
| SDA | Serial Data I/O | Bidirectional open-drain bus line; shares pull-up with other I²C devices; supports multi-master arbitration and collision detection |
Key Features
| Feature | Design Value |
|---|---|
| 256-byte Page Write Mode | Enables burst programming of up to 256 bytes per write cycle, reducing total update time by >95% vs. individual byte writes |
| Hardware Write Protection (WP) | Prevents accidental or malicious overwrites during power-up, brown-out, or firmware crashes without software intervention |
| Internal Device Addressing (A1/A2) | Allows stacking of up to four identical AT24C1024B-PU25 devices on one I²C bus, simplifying multi-module system design |
| Schmitt Trigger Inputs | Provides hysteresis on SCL/SDA lines to reject sub-100 ns noise spikes, ensuring reliable communication in motor-drive or switching-power environments |
| Self-timed Write Cycle | Eliminates need for external write-complete polling delay; host can issue ACK polling after stop condition to verify completion |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Logging |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and user-defined alarm thresholds in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via I²C during boot and runtime reconfiguration. Use Value: Enables field-upgradable control logic without firmware reflashing; retains settings across 100,000+ power cycles. | Use Scenario: Recording sensor offset/gain corrections, patient-specific therapy profiles, and audit trail timestamps in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure, tamper-resistant data vault synchronized with ADC sampling and real-time clock events. Use Value: Meets IEC 62304 Class C data integrity requirements with 40-year retention and hardware write lock during critical procedures. |
| Automotive Body Control Module (BCM) | Smart Energy Meter Firmware Parameters |
Use Scenario: Saving window position limits, mirror fold/unfold presets, and seat memory positions in 12V automotive BCMs. IC Role / Device Role / Timing Role: Low-voltage EEPROM interfaced directly to 5V microcontroller I²C peripheral without level shifters. Use Value: Operates reliably across –40°C to +85°C ambient; withstands load-dump transients due to internal noise filtering and 6.25V absolute max rating. | Use Scenario: Storing tariff schedules, meter ID, CT/PT ratios, and cryptographic keys in ANSI C12.22-compliant utility meters. IC Role / Device Role / Timing Role: Trusted parameter store accessed only during secure boot and authenticated firmware updates. Use Value: Hardware WP pin prevents unauthorized parameter modification; 1Mbit capacity accommodates future firmware extension fields. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C1024D-PU25 | Same memory size and pinout; updated revision with enhanced ESD immunity (±8 kV HBM) and tighter tLOW/tHIGH specs at 1 MHz | Preferred for new designs targeting IEC 61000-4-2 compliance; identical drop-in replacement for AT24C1024B-PU25 | Select AT24C1024D-PU25 for production builds requiring extended reliability validation and latest characterization data. |
| M24C102-RMN6TP | 1 Mbit I²C EEPROM in 8-lead TSSOP; operates 1.7V–5.5V; 400 kHz max clock at 1.7V, 1 MHz at 2.5V+; 3 million write cycles | Surface-mount alternative with smaller footprint; higher endurance but no A1/A2 address pins - limited to single-device per bus | Choose M24C102-RMN6TP when board space is constrained and multi-device bus topology is unnecessary. |
Compared with AT24C1024B-PU25, AT24C1024D-PU25 offers verified ESD robustness for harsh environments, while M24C102-RMN6TP trades cascading capability for compact TSSOP packaging and higher endurance-making each suitable for distinct layout and system architecture priorities.
Availability
AT24C1024B-PU25 is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, automotive body control modules, and smart energy meters requiring stable component supply and long-term obsolescence management.
Supply support for AT24C1024B-PU25 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog components, and nonvolatile memory solutions, with deep expertise in embedded control and data integrity.
The AT24C1024B-PU25 belongs to Microchip's AT24Cxx family of I²C-compatible serial EEPROMs, designed specifically for reliable, low-power, long-life data storage in resource-constrained embedded systems across industrial, medical, and automotive markets.
FAQ
What is the operating voltage range for AT24C1024B-PU25?
The AT24C1024B-PU25 operates from 2.5V to 5.5V, making it compatible with both 3.3V and 5V logic systems. This dual-range specification eliminates the need for external level shifters in mixed-voltage designs and ensures stable I²C communication across common industrial supply rails. The device is not rated for 1.8V operation - that variant is designated AT24C1024B-PU.
Does AT24C1024B-PU25 support multiple devices on the same I²C bus?
Yes, AT24C1024B-PU25 supports up to four devices on a single I²C bus using hardware-configurable A1 and A2 pins. These pins determine the two least-significant bits of the 7-bit device address, enabling unique addressing without software configuration. When left unconnected, both pins are internally pulled low, defaulting to address 0x50 - ideal for single-device systems.
What package type is used for AT24C1024B-PU25?
AT24C1024B-PU25 is packaged in an 8-lead PDIP (Plastic Dual In-line Package) with 0.300" body width, designed for through-hole mounting. This package supports manual prototyping, socket-based testing, and legacy industrial PCB assemblies. It is not available in surface-mount variants like SOIC or TSSOP under this specific part number.
How does the write protect (WP) pin function on AT24C1024B-PU25?
The WP pin on AT24C1024B-PU25 provides hardware-level write inhibition: when tied to VCC, all write operations (byte, page, or erase) are blocked regardless of software commands. When grounded, full write access is enabled. If left floating, the pin is internally pulled low - resulting in write-enabled behavior - though Microchip recommends explicit grounding for deterministic operation.
What is the maximum write speed and page size for AT24C1024B-PU25?
AT24C1024B-PU25 supports a maximum clock frequency of 1 MHz at 2.5V/5V and implements a 256-byte page write mode. Each page write completes in 5 ms typical, allowing up to 256 bytes to be programmed in a single atomic operation. This significantly accelerates bulk data updates compared to sequential byte writes, reducing host CPU overhead and bus occupancy time.
AT24C1024B-PU25 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 550 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT24C1024B-PU25 FAQ
1.How can I place an order for AT24C1024B-PU25 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C1024B-PU25 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C1024B-PU25 reliable?
The price and inventory of AT24C1024B-PU25 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C1024B-PU25 is usually 5 days.
3.What payment methods are accepted for AT24C1024B-PU25?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C1024B-PU25 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C1024B-PU25?
AT24C1024B-PU25 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C1024B-PU25 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C1024B-PU25?
For technical support, including AT24C1024B-PU25 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C1024B-PU25 requirements.
6.How does Aetrix verify that AT24C1024B-PU25 is sourced from the original manufacturer or authorized distributors?
All AT24C1024B-PU25 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C1024B-PU25 meets industry standards.
7.What is the process for return or replacement of AT24C1024B-PU25?
All AT24C1024B-PU25 units undergo pre-shipment inspection (PSI). If there is an issue with AT24C1024B-PU25, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C1024B-PU25 part is unused and in its original packaging.
Return procedure for AT24C1024B-PU25:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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