Microchip Technology AT24C1024B-TH-B
- Part No.:
- AT24C1024B-TH-B
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT24C1024B-TH-B.pdf
- Description:
- IC EEPROM 1MBIT I2C 1MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT24C1024B-TH-B from Microchip Technology (formerly Atmel) is a 1 Mbit (131,072 × 8) two-wire serial EEPROM optimized for low-voltage industrial applications. It operates from 1.8V to 3.6V, supports 400 kHz I²C communication, features hardware write protection via the WP pin, and uses an 8-lead TSSOP package with NiPdAu lead finish.
For engineers reviewing the AT24C1024B-TH-B datasheet, AT24C1024B-TH-B pinout, AT24C1024B-TH-B application, or AT24C1024B-TH-B equivalent, this page delivers verified electrical specs, validated pin functions, real-world use cases in embedded systems, and confirmed alternative parts for supply chain continuity and design flexibility.
Technical Context
The AT24C1024B-TH-B implements a standard I²C-compatible two-wire interface with Schmitt-triggered, noise-filtered inputs. Its internal architecture organizes memory as 512 pages of 256 bytes each, enabling both byte and 256-byte page writes with automatic address incrementing within pages.
Device addressing uses two hardware-configurable pins (A1, A2) to support up to four devices on a shared bus, while the P0 bit in the device address selects between the two 512-Kbyte memory banks. Write cycles are self-timed (5 ms typical), and standby current is 1.0 µA at 1.8V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1,048,576 bits (131,072 × 8), organized as 512 pages × 256 bytes - enables high-density nonvolatile storage in space-constrained designs. |
| Supply Voltage | 1.8V to 3.6V - supports direct integration with modern ultra-low-power microcontrollers and battery-powered systems. |
| I²C Clock Rate | 400 kHz max at 1.8V - ensures reliable timing margins under low-voltage operation without requiring external level shifters. |
| Write Cycle Time | 5 ms typical - defines minimum interval between write commands; critical for firmware update sequencing and data logging burst rates. |
| Endurance | 1,000,000 write cycles per page - guarantees long-term reliability in applications with frequent parameter updates or calibration storage. |
| Data Retention | 40 years at +25°C - ensures configuration and calibration data integrity across product lifetime without refresh. |
| Standby Current | 1.0 µA at VCC = 1.8V - minimizes quiescent power draw in always-on or energy-harvesting edge nodes. |
Pinout & Package
AT24C1024B-TH-B is housed in an 8-lead Thin Shrink Small Outline Package (TSSOP), 4.4 mm body width, with NiPdAu lead finish. Pin 1 is marked by a dot at the top-left corner (viewed from top).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power Supply | Connects to 1.8–3.6V system rail; decoupling capacitor (0.1 µF) required within 10 mm for noise immunity. |
| WP | Hardware Write Protect | Pulled high to VCC to disable all writes; pulled low or left floating (with <3 pF coupling) to enable programming. |
| SCL | Serial Clock Input | Positive-edge clock for data transfer; requires external pull-up resistor (typically 2.2–10 kΩ to VCC). |
| SDA | Serial Data I/O | Open-drain bidirectional line; shares bus with other I²C devices; requires same pull-up as SCL. |
| NC | No Connect | Internally unconnected; must remain unconnected on PCB to avoid unintended leakage or coupling. |
| A1, A2 | Device Address Inputs | Hardwire to VCC/GND or leave floating (internally pulled down) to configure one of four possible I²C addresses (0x50–0x53). |
| GND | Ground Reference | Primary return path for VCC and I/O; connect to clean analog/digital ground plane with low-inductance trace. |
Key Features
| Feature | Design Value |
|---|---|
| 256-byte Page Write Mode | Reduces firmware update time by up to 255× vs. byte writes - essential for fast calibration table uploads or firmware patching. |
| Schmitt Trigger Inputs | Rejects >100 ns noise pulses on SCL/SDA - eliminates spurious start/stop detection in electrically noisy industrial environments. |
| Software Write Protection | WP pin can be toggled high during active firmware execution to prevent accidental overwrites - enhances field reliability. |
| Addressable Cascading | Four devices share one I²C bus using A1/A2 pins - simplifies multi-sensor node designs without additional GPIO or bus expanders. |
| 17-bit Random Addressing | Supports direct access to any byte location without sequential scanning - critical for real-time lookup tables and indexed configuration storage. |
Applications
| Industrial Sensor Calibration Storage | Medical Device Configuration Memory |
|---|---|
Use Scenario: Storing factory-calibrated sensor offsets, gain coefficients, and temperature compensation curves in programmable logic controllers and RTUs. IC Role / Device Role / Timing Role: Nonvolatile parameter repository accessed during boot and runtime via I²C; retains data across power cycles and brownouts. Use Value: Eliminates need for external calibration EEPROMs or costly reprogramming; supports field recalibration with 1Mbit capacity and 1M-cycle endurance. | Use Scenario: Holding patient-specific therapy parameters, device serialization, and regulatory compliance logs in portable infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Secure, tamper-resistant configuration store with hardware write protection (WP pin) to prevent unauthorized parameter changes. Use Value: Meets IEC 62304 Class C software requirements for data integrity; 40-year retention ensures full device lifecycle coverage without backup batteries. |
| Smart Energy Meter Firmware Patch Storage | Automotive Body Control Module Settings |
Use Scenario: Storing encrypted firmware patches and cryptographic keys for secure over-the-air (OTA) updates in ANSI C12.22-compliant smart meters. IC Role / Device Role / Timing Role: Dedicated I²C slave for secure code storage; isolated from main MCU bus during critical update phases using WP control. Use Value: Enables field-deployable security patches without replacing main MCU; 400 kHz I²C speed ensures timely patch loading during meter wake-up windows. | Use Scenario: Saving user preferences (seat position, mirror angle, lighting profiles) and adaptive learning data in automotive BCMs operating at 1.8V logic levels. IC Role / Device Role / Timing Role: Low-voltage EEPROM interfaced directly to 1.8V CAN/LIN microcontroller I/O pins - no level-shifting required. Use Value: Reduces BOM count and PCB area vs. 5V EEPROMs; 1.0 µA standby current extends battery life in key-off monitoring modes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C1024D-SSHM-T | Same 1 Mbit density and 1.8V operation, but in 8-lead SOIC (8S1) package with different pinout (VCC/WP/SCL/SDA on pins 8/7/6/5 vs. TSSOP's 1/2/3/4). | SOIC variant suits legacy through-hole or larger-pitch PCB layouts; not drop-in compatible due to reversed pin order and wider body (3.9 mm vs. TSSOP's 4.4 mm width). | Select when board space allows SOIC and existing layout uses JEDEC SOIC footprint. |
| M24102-BWMN6TP | STMicroelectronics 1 Mbit EEPROM with identical 1.8–3.6V range and 400 kHz I²C, but uses different device addressing (A0/A1 only) and lacks P0 bank-select bit. | Compatible for basic byte/page reads/writes, but cannot replicate AT24C1024B-TH-B's dual-bank addressing scheme used in advanced firmware partitioning. | Select for cost-sensitive designs where bank-select functionality is unused and SOIC/TSSOP mechanical compatibility is verified. |
Compared with AT24C1024D-SSHM-T and M24102-BWMN6TP, the AT24C1024B-TH-B offers unique TSSOP packaging with optimized pinout for dense routing, plus P0-based memory banking - making it preferred for new compact designs requiring flexible firmware partitioning and minimal board area.
Availability
AT24C1024B-TH-B is available at Aetrix Electronics and suitable for industrial sensor nodes, medical diagnostics equipment, and automotive body control modules requiring stable component supply and long-term obsolescence management.
Supply support for AT24C1024B-TH-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and continues to manufacture, qualify, and support the AT24Cxx family of serial EEPROMs with full backward compatibility and extended product longevity.
The AT24C1024B-TH-B belongs to Microchip's industrial-grade serial EEPROM product line, designed specifically for robust, low-power nonvolatile storage in harsh environments - including extended temperature operation (–40°C to +85°C) and high-reliability data retention.
FAQ
What is the maximum I²C clock frequency supported by the AT24C1024B-TH-B at 1.8V?
The AT24C1024B-TH-B supports a maximum I²C clock frequency of 400 kHz when operating at 1.8V. This is specified in the AC Characteristics table under fSCL for the 1.8-volt column. The device does not support 1 MHz operation at 1.8V - that rate applies only to 2.5V and 5.0V supply conditions, which are not applicable to the AT24C1024B-TH-B variant.
Does the AT24C1024B-TH-B require external pull-up resistors on SCL and SDA lines?
Yes, the AT24C1024B-TH-B requires external pull-up resistors on both SCL and SDA lines because its I/O structure is open-drain. Typical values range from 2.2 kΩ to 10 kΩ to VCC, depending on bus capacitance and desired rise time. The device's internal Schmitt triggers ensure noise immunity, but external pull-ups are mandatory for proper I²C bus signaling.
How many devices can share the same I²C bus with the AT24C1024B-TH-B?
Up to four AT24C1024B-TH-B devices can share a single I²C bus using the A1 and A2 address input pins. These pins configure the two least-significant bits of the 7-bit I²C slave address, yielding four unique addresses: 0x50, 0x51, 0x52, and 0x53. The WP pin and NC pin do not affect addressing.
What is the function of the NC pin on the AT24C1024B-TH-B TSSOP package?
The NC (No Connect) pin on the AT24C1024B-TH-B TSSOP package is internally unconnected and must remain unconnected on the PCB. It serves as a mechanical placeholder to maintain pin spacing and package symmetry. Connecting it to any voltage or signal risks introducing leakage paths or capacitive coupling that could degrade noise immunity on adjacent pins like SCL or SDA.
Can the AT24C1024B-TH-B retain data for 40 years under industrial temperature conditions?
The 40-year data retention specification for the AT24C1024B-TH-B is rated at +25°C ambient. At the full industrial temperature range (–40°C to +85°C), retention is characterized but not guaranteed for 40 years; actual retention decreases with elevated temperature and is governed by Arrhenius kinetics. For mission-critical applications above 25°C, derating or periodic verification is recommended.
AT24C1024B-TH-B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 550 ns
- Voltage - Supply:
- 1.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT24C1024B-TH-B FAQ
1.How can I place an order for AT24C1024B-TH-B through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C1024B-TH-B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C1024B-TH-B reliable?
The price and inventory of AT24C1024B-TH-B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C1024B-TH-B is usually 5 days.
3.What payment methods are accepted for AT24C1024B-TH-B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C1024B-TH-B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C1024B-TH-B?
AT24C1024B-TH-B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C1024B-TH-B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C1024B-TH-B?
For technical support, including AT24C1024B-TH-B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C1024B-TH-B requirements.
6.How does Aetrix verify that AT24C1024B-TH-B is sourced from the original manufacturer or authorized distributors?
All AT24C1024B-TH-B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C1024B-TH-B meets industry standards.
7.What is the process for return or replacement of AT24C1024B-TH-B?
All AT24C1024B-TH-B units undergo pre-shipment inspection (PSI). If there is an issue with AT24C1024B-TH-B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C1024B-TH-B part is unused and in its original packaging.
Return procedure for AT24C1024B-TH-B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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