Microchip Technology AT24C128BN-SH-T
- Part No.:
- AT24C128BN-SH-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT24C128BN-SH-T.pdf
- Description:
- IC EEPROM 128KBIT I2C 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,443
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT24C128BN-SH-T from Microchip Technology (formerly Atmel) is a 128 Kbit I²C-compatible serial EEPROM organized as 16,384 × 8 bits, operating from 1.8 V to 5.5 V, featuring 64-byte page write mode, hardware write protection via WP pin, and 1 MHz (5.5 V) / 400 kHz (1.8 V) interface speed. It is used in industrial control modules for nonvolatile parameter storage with low-power retention.
For engineers reviewing the AT24C128BN-SH-T datasheet, AT24C128BN-SH-T pinout, AT24C128BN-SH-T application, or AT24C128BN-SH-T equivalent, this page delivers verified electrical specs, JEDEC SOIC-8 package details, noise-suppressed I²C timing, endurance (1M cycles), and real-world use cases in embedded systems requiring field-updatable configuration data.
Technical Context
The AT24C128BN-SH-T implements a two-wire serial interface with Schmitt-triggered, filtered SDA/SCL inputs for robust noise immunity in electrically noisy environments. Its internal address counter supports current-address, random-address, and sequential reads, while cascading up to eight devices on one bus is enabled by hardwired A2–A0 pins.
Write operations include byte and 64-byte page modes with self-timed internal write cycles (≤5 ms), and acknowledge polling allows host synchronization without fixed delays. Data security is enforced via hardware write protect (WP pin tied to VCC) and software-controlled locking of memory segments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 131,072 bits (16,384 × 8), enabling storage of firmware calibration tables or device-specific configuration registers |
| Supply Voltage Range | 1.8 V to 5.5 V - supports direct interfacing with 1.8 V microcontrollers and legacy 5 V systems without level shifting |
| I²C Clock Frequency | Up to 1 MHz at 5.5 V; 400 kHz at 1.8 V - ensures compatibility with standard and fast-mode I²C controllers |
| Page Write Capacity | 64 bytes per page - reduces write transaction overhead and improves efficiency when updating contiguous configuration blocks |
| Endurance & Retention | 1,000,000 write cycles and 40-year data retention - suitable for applications requiring frequent field updates over product lifetime |
| Operating Temperature | −40°C to +85°C - validated for industrial-grade operation in programmable logic controllers and sensor transmitters |
| Input Capacitance | SDA: 8 pF max; SCL/A0–A1: 6 pF max - enables reliable high-speed signaling on PCB traces up to 15 cm without signal integrity degradation |
Pinout & Package
AT24C128BN-SH-T is packaged in an 8-lead JEDEC SOIC (package code 8S1), 3.9 mm × 4.9 mm body, 1.27 mm pitch, NiPdAu lead finish - compatible with standard reflow profiles and automated assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A2 | Hardware Device Address Inputs | Enable up to eight AT24C128BN-SH-T devices on one I²C bus; must be hardwired to GND or VCC for deterministic addressing |
| SDA | Serial Data Line | Bidirectional open-drain I/O; requires external pull-up resistor (typically 1.3 kΩ at 2.5/5.5 V, 10 kΩ at 1.8 V) |
| SCL | Serial Clock Input | Positive-edge clock input for data latching; negative-edge for data output - defines I²C timing compliance |
| WP | Write Protect Control | Active-high hardware lock: tied to VCC disables all writes; floating defaults to GND (enabled), but external tie recommended |
| GND | Ground Reference | Primary return path for VCC, SDA, SCL, and WP - must be low-impedance connection to avoid noise coupling into I²C lines |
| VCC | Power Supply | Single supply input supporting 1.8–5.5 V; powers internal HV pump for EEPROM programming and logic circuitry |
Key Features
| Feature | Design Value |
|---|---|
| Noise-immune I²C interface | Schmitt-triggered, filtered SDA/SCL inputs suppress EMI-induced glitches - eliminates spurious start/stop detection in motor-drive environments |
| Flexible write protection | Hardware (WP pin) and software (address-range locking) protection - prevents accidental overwrites during firmware updates or brown-out recovery |
| Low-power standby | 1.0 µA max at 1.8 V - extends battery life in portable instrumentation and wireless sensor nodes between configuration reads |
| Robust page write architecture | 64-byte pages with automatic address wrap-around - simplifies firmware design for block-based parameter storage without manual boundary checks |
| Industrial temperature grade | −40°C to +85°C operation - qualified for deployment in DIN-rail mounted PLCs and outdoor environmental monitoring hardware |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing user-defined I/O mapping, PID tuning parameters, and alarm thresholds in modular programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via I²C during boot and runtime reconfiguration. Use Value: Enables field-upgradable logic behavior without firmware reflashing; 1M endurance supports daily parameter adjustments over 10+ years. |
Use Scenario: Retaining factory-calibrated sensor offsets and gain coefficients in portable blood glucose meters and infusion pumps. IC Role / Device Role / Timing Role: Secure, tamper-resistant data vault with hardware write protection activated during production test. Use Value: Ensures regulatory compliance (IEC 62304) by preventing unauthorized modification of safety-critical calibration values. |
| Smart Energy Meter Firmware Parameters | Automotive Body Control Module Settings |
Use Scenario: Holding tariff schedules, demand-response thresholds, and metering constants updated remotely via HAN communication. IC Role / Device Role / Timing Role: I²C slave device interfaced to metrology SoC; accessed during power-up and OTA update verification. Use Value: 40-year data retention guarantees accurate billing data persistence across meter lifetime (>15 years in-field). |
Use Scenario: Storing seat position presets, mirror angles, and lighting profiles in automotive body control units (BCUs). IC Role / Device Role / Timing Role: Low-voltage EEPROM interfaced to 3.3 V CAN microcontroller; retains settings through ignition cycling. Use Value: 1.8 V operation allows direct connection to MCU I/O banks without level shifters - reducing BOM cost and board space. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M24128-BWMN6TP | STMicroelectronics 128 Kbit EEPROM; identical 16,384 × 8 organization, 1.8–5.5 V, 1 MHz I²C, but uses different internal page buffer management | Same industrial temperature range (−40°C to +85°C); slightly higher standby current (2 µA @ 1.8 V vs. 1 µA) | Drop-in replacement for AT24C128BN-SH-T in SOIC-8 footprint; verify WP pin behavior matches system-level write-lock policy |
| BR24G128FJ-3GE2 | Rohm 128 Kbit EEPROM; same voltage range and I²C speed, but features built-in error correction (ECC) and enhanced write-cycle reliability | Extended qualification for automotive AEC-Q100 Grade 2 (−40°C to +105°C); not required for industrial-only designs | Preferred where extended temperature margin or ECC-assisted data integrity is mandated; requires validation of ECC enable/disable sequence |
Compared with M24128-BWMN6TP and BR24G128FJ-3GE2, the AT24C128BN-SH-T offers lowest standby current and proven interoperability with legacy Atmel/Microchip ecosystem tools, while the alternatives provide either footprint compatibility or automotive-grade robustness at minor trade-offs in power or feature set.
Availability
AT24C128BN-SH-T is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, smart metering, and automotive body electronics requiring stable component supply and long-term lifecycle support.
Supply support for AT24C128BN-SH-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full technical and manufacturing continuity for the AT24Cxx EEPROM family. The company specializes in secure, reliable microcontrollers and memory solutions for industrial and automotive markets.
The AT24C128BN-SH-T belongs to Microchip's serial EEPROM product line, designed specifically for low-power, high-reliability nonvolatile storage in resource-constrained embedded systems where I²C simplicity and proven field longevity are critical.
FAQ
What is the maximum I²C clock frequency supported by the AT24C128BN-SH-T?
The AT24C128BN-SH-T supports up to 1 MHz I²C clock frequency when VCC ≥ 2.5 V, and 400 kHz when operating at 1.8 V. These speeds are guaranteed across the full industrial temperature range (−40°C to +85°C) and are defined in Table 5-3 of the official datasheet. The AT24C128BN-SH-T does not support standard-mode-plus (1 MHz) at 1.8 V - that capability is reserved for higher-voltage operation only.
Does the AT24C128BN-SH-T require external pull-up resistors on SDA and SCL lines?
Yes, the AT24C128BN-SH-T requires external pull-up resistors on both SDA and SCL lines because its I²C interface uses open-drain outputs. Recommended values are 1.3 kΩ for 2.5 V/5.5 V operation and 10 kΩ for 1.8 V operation, as specified in the AC characteristics section. Without proper pull-ups, the AT24C128BN-SH-T will fail to generate valid I²C start/stop conditions or acknowledge addresses.
How many AT24C128BN-SH-T devices can share the same I²C bus?
Up to eight AT24C128BN-SH-T devices can share a single I²C bus using hardware address pins A2, A1, and A0. Each combination of hardwired GND/VCC states on these pins yields a unique 3-bit device address, allowing distinct addressing within the standard 7-bit I²C protocol. Floating A0–A2 pins default to GND but are not recommended due to noise susceptibility - the AT24C128BN-SH-T datasheet explicitly advises hardwiring.
What is the purpose of the WP (Write Protect) pin on the AT24C128BN-SH-T?
The WP pin on the AT24C128BN-SH-T provides hardware-level write inhibition: when pulled high to VCC, all write operations (byte, page, and erase) are blocked regardless of software commands. When grounded, normal write functionality is enabled. The AT24C128BN-SH-T also supports software write protection for specific memory blocks, but WP offers unconditional, power-on-default security against accidental writes during system initialization or fault conditions.
Is the AT24C128BN-SH-T RoHS-compliant and halogen-free?
Yes, the AT24C128BN-SH-T is lead-free and halogen-free, meeting RoHS Directive 2011/65/EU requirements. Its NiPdAu (Nickel-Palladium-Gold) lead finish ensures solderability, corrosion resistance, and wire-bond compatibility. This compliance is confirmed in the "Features" section of the datasheet and applies to all package variants including the SOIC-8 (8S1) form used in AT24C128BN-SH-T.
AT24C128BN-SH-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 550 ns
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT24C128BN-SH-T FAQ
1.How can I place an order for AT24C128BN-SH-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C128BN-SH-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C128BN-SH-T reliable?
The price and inventory of AT24C128BN-SH-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C128BN-SH-T is usually 5 days.
3.What payment methods are accepted for AT24C128BN-SH-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C128BN-SH-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C128BN-SH-T?
AT24C128BN-SH-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C128BN-SH-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C128BN-SH-T?
For technical support, including AT24C128BN-SH-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C128BN-SH-T requirements.
6.How does Aetrix verify that AT24C128BN-SH-T is sourced from the original manufacturer or authorized distributors?
All AT24C128BN-SH-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C128BN-SH-T meets industry standards.
7.What is the process for return or replacement of AT24C128BN-SH-T?
All AT24C128BN-SH-T units undergo pre-shipment inspection (PSI). If there is an issue with AT24C128BN-SH-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C128BN-SH-T part is unused and in its original packaging.
Return procedure for AT24C128BN-SH-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT24C128BN-SH-T Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
