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Microchip Technology AT24C128C-MAPD-E
- Part No.:
- AT24C128C-MAPD-E
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT24C128C-MAPD-E.pdf
- Description:
- IC EEPROM 128KBIT I2C 8UDFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,191
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Product details
Overview
AT24C128C-MAPD-E from Microchip Technology is an AEC-Q100 Grade 1 automotive serial EEPROM with 128-Kbit (16,384 × 8) memory organization, I²C-compatible two-wire interface operating up to 400 kHz, and rated for -40°C to +125°C operation. It features hardware write protection (WP pin), 64-byte page write capability, and ultra-low standby current of 6 μA max at 5.0 V - deployed in body control modules, airbag controllers, and powertrain sensors requiring nonvolatile configuration storage.
For engineers reviewing the AT24C128C-MAPD-E datasheet, AT24C128C-MAPD-E pinout, AT24C128C-MAPD-E application, or AT24C128C-MAPD-E equivalent, this page delivers verified package mapping (8-lead SOIC), confirmed I²C timing compliance (tWR ≤ 5 ms, tAA ≤ 4.5 μs), endurance (1M cycles), data retention (100 years), and automotive-grade voltage range (2.5V–5.5V).
Technical Context
The AT24C128C-MAPD-E operates as a slave device on an I²C bus, using Schmitt-triggered, filtered SDA/SCL inputs for noise immunity in harsh automotive environments. Its internal architecture includes a 14-bit address counter, hardware address comparator (A0–A2), and high-voltage generation circuit enabling byte/page writes without external programming voltage.
It supports standard-mode (100 kHz) and fast-mode (400 kHz) I²C protocols with strict AC timing compliance: tLOW ≥ 1.2 μs, tHIGH ≥ 0.6 μs, and tBUF ≥ 1.2 μs. The WP pin provides hardware-level write protection, and all address pins default to GND via internal strong pull-downs - eliminating floating-input risk when unconnected.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8), organized in 256 pages of 64 bytes - enables efficient firmware parameter storage with partial-page write flexibility. |
| Interface | I²C two-wire (SDA/SCL), 400 kHz fast mode - compatible with microcontroller I²C peripherals without protocol translation. |
| Supply Voltage | 2.5 V to 5.5 V (Grade 1) - supports direct connection to 3.3 V or 5 V automotive domains without level-shifting. |
| Operating Temp | -40°C to +125°C - qualified per AEC-Q100 Grade 1 for under-hood and transmission control unit deployment. |
| Write Endurance | 1,000,000 cycles - ensures reliable recalibration logging over full vehicle service life (15+ years). |
| Data Retention | 100 years at 55°C - guarantees long-term integrity of safety-critical calibration data without refresh. |
| Standby Current | 6 μA max at 5.0 V - minimizes parasitic drain in always-on vehicle subsystems (e.g., gateway ECUs). |
| Write Cycle Time | ≤ 5 ms maximum - enables deterministic timeout handling in real-time safety firmware. |
Pinout & Package
AT24C128C-MAPD-E is supplied in an 8-lead SOIC package (3.9 mm × 4.9 mm, 1.27 mm pitch), pin-compatible with industry-standard I²C EEPROM footprints and suitable for reflow assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Hardware Device Address Input | Configures LSB of 7-bit I²C slave address (1010xxx); pulled down internally if unconnected - enables up to 8 devices on one bus. |
| A1 | Hardware Device Address Input | Configures middle bit of slave address; same internal pull-down behavior as A0 - ensures deterministic addressing without external resistors. |
| A2 | Hardware Device Address Input | Configures MSB of slave address; identical robust pull-down design - eliminates need for external biasing in cost-sensitive designs. |
| GND | Power Ground Reference | System return path for VCC and I/O; must be connected directly to low-impedance chassis or PCB ground plane. |
| SDA | Open-Drain Bidirectional Data Line | Transfers command/data/ACK/NACK; requires external pull-up (≤10 kΩ) - shares bus with other I²C slaves via wire-OR logic. |
| SCL | Input Clock Line | Controls data sampling timing; rising edge latches input, falling edge outputs data - must be pulled high or driven actively. |
| WP | Hardware Write-Protection Enable | Low = write enabled; high = full-array protection; internally pulled down - prevents accidental overwrites during power transients. |
| VCC | Power Supply Input | Supplies core logic and EEPROM array; slew rate ≤0.1 V/μs required for reliable POR - supports 2.5–5.5 V automotive rails. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Grade 1 qualification | Validated for -40°C to +125°C operation with extended reliability testing - meets functional safety requirements for ASIL-B systems. |
| 64-byte page write with partial writes | Allows writing 1–64 bytes per transaction without erasing adjacent data - reduces firmware overhead and wear leveling complexity. |
| Schmitt-triggered, filtered I/O | Rejects EMI-induced glitches on SDA/SCL in noisy 12 V automotive harnesses - eliminates need for external RC filtering. |
| Internal strong pull-down on A0/A1/A2/WP | Guarantees known logic state when pins float - removes dependency on external biasing and simplifies PCB layout. |
| Self-timed 5 ms write cycle | Hardware-managed erase/write sequence with no external timing control - enables deterministic software polling or interrupt-driven completion. |
| Green RoHS-compliant packaging | Lead-free, halide-free 8-lead SOIC - satisfies global automotive environmental compliance (ELV, IMDS, REACH). |
Applications
| Body Control Module (BCM) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
|
Use Scenario: Storing seat position, mirror angle, and lighting presets across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile configuration register for user-customizable settings accessed via MCU I²C at boot and runtime. Use Value: Enables zero-latency recall of driver preferences without battery-backed SRAM - supported by 100-year data retention and 1M write cycles. |
Use Scenario: Saving camera calibration offsets and radar sensor compensation tables after factory alignment. IC Role / Device Role / Timing Role: Secure, write-protected storage for safety-critical calibration parameters updated only during diagnostic sessions. Use Value: WP pin hardware lock prevents field corruption; Grade 1 temperature rating ensures integrity during engine-off thermal soak. |
| Engine Control Unit (ECU) | Electric Power Steering (EPS) |
|
Use Scenario: Logging fault codes and operational counters for OBD-II diagnostics and warranty analysis. IC Role / Device Role / Timing Role: Event-triggered write buffer for intermittent error records, accessed asynchronously via I²C. Use Value: Ultra-low 6 μA standby current avoids draining 12 V battery during prolonged parking; 5 ms write time fits within CAN message latency budgets. |
Use Scenario: Storing torque sensor zero-point offsets and motor phase calibration values post-assembly. IC Role / Device Role / Timing Role: Factory-programmed reference data storage with hardware write-disable to prevent field tampering. Use Value: Internal WP pull-down ensures protection even if trace is severed; AEC-Q100 Grade 1 validates operation inside steering column housing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M24C128-DFMN6TP/K | Same 128-Kbit size, I²C 400 kHz, but Grade 3 (-40°C to +85°C); lower max VCC (5.5 V) and higher ISB (10 μA). | Limited to cabin-mounted modules (e.g., infotainment), not under-hood use. | Select when cost sensitivity outweighs extended temperature needs and system VCC stays ≤5.5 V. |
| ON Semiconductor CAT24C128WI-GT3 | Identical Grade 1 rating and 128-Kbit density, but uses 8-lead TSSOP (3 × 4.4 mm); slightly higher tWR (6 ms). | Requires PCB footprint change; acceptable where board space is constrained and 1 ms longer write time is tolerable. | Choose for space-constrained layouts where TSSOP's smaller footprint offsets rework effort. |
Compared with AT24C128C-MAPD-E, the ST part trades automotive temperature range for lower cost and the ON part swaps SOIC for TSSOP to save area - neither offers the same combination of Grade 1 reliability, SOIC compatibility, and 5 ms write timing in a single package.
Availability
AT24C128C-MAPD-E is available at Aetrix Electronics and suitable for automotive body electronics, ADAS calibration storage, and powertrain diagnostics requiring stable component supply across extended temperature and long product lifecycles.
Supply support for AT24C128C-MAPD-E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with ISO/TS 16949-certified automotive manufacturing.
The AT24C128C-MAPD-E belongs to Microchip's AEC-Q100-qualified serial EEPROM product line, designed specifically for automotive subsystems demanding high reliability, extended temperature operation, and I²C interoperability.
FAQ
What is the maximum I²C clock frequency supported by the AT24C128C-MAPD-E?
The AT24C128C-MAPD-E supports I²C fast mode up to 400 kHz, with guaranteed AC timing compliance including tLOW ≥ 1.2 μs and tHIGH ≥ 0.6 μs. This allows high-throughput parameter updates in automotive ECUs without compromising signal integrity - fully validated per DS20006270B Section 4.4.
Does the AT24C128C-MAPD-E require external pull-up resistors on SDA and SCL lines?
Yes, the AT24C128C-MAPD-E requires external pull-up resistors on both SDA and SCL lines, with recommended values ≤10 kΩ. The SDA pin is open-drain and must be pulled high to enable bidirectional communication; SCL may be pulled up or actively driven - specified in DS20006270B Section 2.3 and 2.4.
How does the write-protect (WP) pin function on the AT24C128C-MAPD-E?
When the WP pin is driven high (VCC), the AT24C128C-MAPD-E inhibits all write operations to its entire memory array; when low (GND), normal writes are permitted. If left unconnected, WP is internally pulled down to GND - ensuring default writability while preventing spurious protection activation due to noise.
Is the AT24C128C-MAPD-E pin-compatible with other 8-lead SOIC EEPROMs?
Yes, the AT24C128C-MAPD-E uses standard 8-lead SOIC pinout (A0–A2, GND, SDA, SCL, WP, VCC) matching JEDEC MS-012, enabling drop-in replacement for legacy 128-Kbit I²C EEPROMs like AT24C128B - provided voltage, timing, and AEC-Q100 requirements align.
What is the endurance and data retention specification for the AT24C128C-MAPD-E?
The AT24C128C-MAPD-E guarantees 1,000,000 write cycles and 100 years of data retention at 55°C, as validated per AEC-Q100 stress testing and EEPROM cell characterization - documented in DS20006270B Table 4-6 and confirmed for Grade 1 operation.
AT24C128C-MAPD-E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT24C128C-MAPD-E FAQ
1.How can I place an order for AT24C128C-MAPD-E through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C128C-MAPD-E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C128C-MAPD-E reliable?
The price and inventory of AT24C128C-MAPD-E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C128C-MAPD-E is usually 5 days.
3.What payment methods are accepted for AT24C128C-MAPD-E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C128C-MAPD-E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C128C-MAPD-E?
AT24C128C-MAPD-E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C128C-MAPD-E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C128C-MAPD-E?
For technical support, including AT24C128C-MAPD-E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C128C-MAPD-E requirements.
6.How does Aetrix verify that AT24C128C-MAPD-E is sourced from the original manufacturer or authorized distributors?
All AT24C128C-MAPD-E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C128C-MAPD-E meets industry standards.
7.What is the process for return or replacement of AT24C128C-MAPD-E?
All AT24C128C-MAPD-E units undergo pre-shipment inspection (PSI). If there is an issue with AT24C128C-MAPD-E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C128C-MAPD-E part is unused and in its original packaging.
Return procedure for AT24C128C-MAPD-E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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