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Microchip Technology AT24C128C-MAPD-T

Name: AT24C128C-MAPD-T
Brand: Microchip Technology
SKU: AT24C128C-MAPD-T
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AT24C128C-MAPD-T

Manufacturer:: Microchip Technology

Category:: Memory

Package:: 8-UFDFN Exposed Pad

Datasheet:: AT24C128C-MAPD-T.pdf

Description:: IC EEPROM 128KBIT I2C 8UDFN

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Product details

Overview

AT24C128C-MAPD-T from Microchip Technology is an AEC-Q100 Grade 1 automotive serial EEPROM with 128-Kbit (16,384 × 8) memory organization, I²C-compatible two-wire interface operating up to 400 kHz, and rated for -40°C to +125°C operation. It features hardware write protection (WP pin), 64-byte page write capability, and ultra-low standby current (≤6 μA at 5.0 V). It is used in engine control units, ADAS sensor modules, and automotive body electronics for storing calibration data and configuration parameters.

For engineers reviewing the AT24C128C-MAPD-T datasheet, AT24C128C-MAPD-T pinout, AT24C128C-MAPD-T application, or AT24C128C-MAPD-T equivalent, key selection criteria include Grade 1 temperature compliance, I²C fast-mode timing compatibility, WP-enabled hardware data protection, and SOIC-8 package suitability for automotive PCB layouts requiring reflow reliability and thermal cycling endurance.

Technical Context

The AT24C128C-MAPD-T operates as a slave device on an I²C bus, using Schmitt-triggered SDA/SCL inputs with integrated noise filtering. Its internal architecture includes a 14-bit address counter, column/row decoders, and high-voltage generation circuitry enabling byte and page writes without external charge pumps.

It supports standard-mode (100 kHz) and fast-mode (400 kHz) I²C protocols with strict tLOW/tHIGH timing compliance, ACK/NACK handshaking, and software reset via SCL clocking. Memory is organized into 256 pages of 64 bytes each, with self-timed write cycles completing in ≤5 ms and full-array write protection activated by pulling WP to VCC.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Size	128 Kbit (16,384 × 8), organized as 256 pages × 64 bytes - enables efficient firmware parameter storage with page-level write granularity.
Interface	I²C two-wire serial (SCL/SDA), 400 kHz fast mode - compatible with modern microcontrollers without requiring additional level-shifting or protocol translation.
Supply Voltage	2.5 V to 5.5 V (Grade 1) - supports direct connection to 3.3 V or 5 V automotive power domains without regulators.
Operating Temperature	-40°C to +125°C (AEC-Q100 Grade 1) - qualified for under-hood and transmission-control applications with full functionality across extreme thermal profiles.
Write Endurance	1,000,000 cycles - ensures reliable logging of vehicle diagnostics or adaptive learning data over full vehicle lifetime.
Data Retention	100 years at 55°C - guarantees long-term integrity of safety-critical calibration tables without refresh mechanisms.
Standby Current	≤6 μA at VCC = 5.0 V - minimizes parasitic drain in always-on automotive modules such as gateway ECUs.
Write Protection	Hardware WP pin - provides deterministic, glitch-immune lockout of memory writes during power transients or ECU resets.

Pinout & Package

AT24C128C-MAPD-T is supplied in an 8-lead SOIC package (body width 3.9 mm, JEDEC MS-012), optimized for automotive reflow profiles and mechanical robustness. Pin 1 is A0 (top-left corner when notch faces up).

Pin/Terminal	Circuit Role	Design Meaning
A0	Device Address Input	Hardwired to GND or VCC to configure one of eight possible I²C slave addresses; internally pulled down if floating - enables multi-device bus topology without external resistors.
A1	Device Address Input	Second address bit; same pull-down behavior as A0 - allows up to eight AT24C128C-MAPD-T devices on a single I²C bus.
A2	Device Address Input	Third address bit; identical biasing and routing requirements as A0/A1 - supports scalable memory expansion in distributed automotive networks.
GND	Ground Reference	System ground return path; must be low-impedance and co-located with host MCU ground to minimize noise coupling into SDA/SCL lines.
SDA	Serial Data I/O	Open-drain bidirectional line; requires external pull-up resistor ≤10 kΩ - interfaces directly with I²C masters without level translators.
SCL	Serial Clock Input	Input-only clock line; must be pulled high externally - synchronizes all read/write transfers and defines timing margins per I²C specification.
WP	Write-Protect Control	Active-high hardware lock; tied to VCC to disable all writes - prevents corruption during brown-out, reset, or firmware update sequences.
VCC	Power Supply	2.5–5.5 V supply input; includes internal POR circuit with 100 µs tPUP delay - ensures deterministic initialization after power ramp.

Key Features

Feature	Design Value
AEC-Q100 Grade 1 qualification	Validated for -40°C to +125°C operation with full electrical testing across temperature - eliminates need for derating or additional thermal validation in engine bay designs.
64-byte page write mode	Enables burst programming of up to 64 bytes per write cycle without inter-byte delays - reduces firmware update time by >90% vs. byte-write methods.
Schmitt-triggered inputs with noise filtering	Rejects >100 ns spikes on SDA/SCL - maintains I²C communication integrity in high-EMI environments like alternator proximity or motor drive zones.
Ultra-low standby current (≤6 μA)	Minimizes quiescent power draw in always-on modules - extends battery life in parked-state ADAS cameras or telematics gateways.
Hardware write protection (WP pin)	Provides fail-safe memory lock independent of firmware state - prevents accidental overwrite during bootloader execution or voltage sag events.
100-year data retention at 55°C	Guarantees nonvolatile storage integrity over full vehicle service life without periodic refresh - critical for regulatory-compliant event data recorders (EDR).

Applications

Engine Control Unit (ECU)	Advanced Driver Assistance Systems (ADAS)
Use Scenario: Storing fuel injection timing maps, knock sensor calibration offsets, and OBD-II diagnostic trouble codes (DTCs) that persist across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile configuration storage slave on I²C bus, accessed asynchronously by main MCU during boot and runtime. Use Value: Enables zero-latency recall of validated engine parameters after cold start; WP pin prevents corruption during cranking-induced voltage dips.	Use Scenario: Retaining camera lens distortion coefficients, radar object classification thresholds, and lane detection model version metadata in front-facing ADAS cameras. IC Role / Device Role / Timing Role: Dedicated calibration data repository with deterministic write latency (≤5 ms) and immunity to CAN bus noise coupling. Use Value: Ensures consistent perception accuracy across vehicle lifetime; Grade 1 rating supports operation behind windshield in direct sunlight exposure.
Body Control Module (BCM)	Electric Power Steering (EPS)
Use Scenario: Saving user-configurable settings (mirror position, seat memory, lighting preferences) and door lock actuator wear counters. IC Role / Device Role / Timing Role: Low-power I²C slave supporting infrequent writes and frequent reads during vehicle entry/exit sequences. Use Value: 6 μA standby current extends battery reserve capacity; 1M-cycle endurance exceeds 15-year ownership usage models.	Use Scenario: Storing torque sensor zero-point compensation values, motor phase resistance calibration, and fault history logs for steering assist motors. IC Role / Device Role / Timing Role: Safety-relevant parameter store interfaced via isolated I²C to EPS MCU, with WP pin asserted during motor activation. Use Value: Prevents unintended calibration erasure during high-current transients; AEC-Q100 Grade 1 ensures reliability at steering rack temperatures.

Engine Control Unit (ECU)

Advanced Driver Assistance Systems (ADAS)

Use Scenario: Storing fuel injection timing maps, knock sensor calibration offsets, and OBD-II diagnostic trouble codes (DTCs) that persist across ignition cycles.

IC Role / Device Role / Timing Role: Nonvolatile configuration storage slave on I²C bus, accessed asynchronously by main MCU during boot and runtime.

Use Value: Enables zero-latency recall of validated engine parameters after cold start; WP pin prevents corruption during cranking-induced voltage dips.

Use Scenario: Retaining camera lens distortion coefficients, radar object classification thresholds, and lane detection model version metadata in front-facing ADAS cameras.

IC Role / Device Role / Timing Role: Dedicated calibration data repository with deterministic write latency (≤5 ms) and immunity to CAN bus noise coupling.

Use Value: Ensures consistent perception accuracy across vehicle lifetime; Grade 1 rating supports operation behind windshield in direct sunlight exposure.

Body Control Module (BCM)

Electric Power Steering (EPS)

Use Scenario: Saving user-configurable settings (mirror position, seat memory, lighting preferences) and door lock actuator wear counters.

IC Role / Device Role / Timing Role: Low-power I²C slave supporting infrequent writes and frequent reads during vehicle entry/exit sequences.

Use Value: 6 μA standby current extends battery reserve capacity; 1M-cycle endurance exceeds 15-year ownership usage models.

Use Scenario: Storing torque sensor zero-point compensation values, motor phase resistance calibration, and fault history logs for steering assist motors.

IC Role / Device Role / Timing Role: Safety-relevant parameter store interfaced via isolated I²C to EPS MCU, with WP pin asserted during motor activation.

Use Value: Prevents unintended calibration erasure during high-current transients; AEC-Q100 Grade 1 ensures reliability at steering rack temperatures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ST M24C128-DFMN6TP	Same 128-Kbit size and I²C interface, but AEC-Q100 Grade 2 (-40°C to +105°C); no WP pin - relies on software write protection.	Limited to cabin-mounted modules (e.g., infotainment) where ambient temperature does not exceed +105°C.	Select when cost sensitivity outweighs under-hood temperature margin and hardware write lock is not required.
ON Semiconductor CAT24C128WI-GT3	Identical Grade 1 rating and SOIC-8 package, but supports 1 MHz ultra-fast-mode I²C; higher ICC (3.5 mA max during write).	Suitable for high-throughput logging systems (e.g., data recorders) needing faster write throughput than AT24C128C-MAPD-T's 400 kHz limit.	Choose when system-level I²C bus speed exceeds 400 kHz and additional active current budget is available.

Compared with ST M24C128-DFMN6TP and CAT24C128WI-GT3, the AT24C128C-MAPD-T uniquely combines Grade 1 thermal compliance, hardware WP pin, and 400 kHz timing margin - making it optimal for safety-critical, thermally demanding automotive nodes where deterministic write protection and extended temperature operation are mandatory.

Availability

AT24C128C-MAPD-T is available at Aetrix Electronics and suitable for engine control units, ADAS sensor modules, and body control modules requiring stable component supply across extended automotive production lifecycles.

Supply support for AT24C128C-MAPD-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with broad automotive qualification expertise and ISO/TS 16949-certified manufacturing.

The AT24C128C-MAPD-T belongs to Microchip's AEC-Q100-qualified serial EEPROM product line, designed specifically for automotive subsystems requiring guaranteed data integrity, extended temperature operation, and I²C protocol robustness.

FAQ

What is the maximum I²C clock frequency supported by the AT24C128C-MAPD-T?

The AT24C128C-MAPD-T supports I²C fast mode up to 400 kHz, with guaranteed AC timing compliance including tLOW ≥1,200 ns and tHIGH ≥600 ns at VCC = 2.5 V. It does not support ultra-fast-mode (1 MHz) - attempting higher frequencies may cause ACK failures or data corruption. The AT24C128C-MAPD-T datasheet specifies these limits in Table 4-3 under AC Characteristics.

Does the AT24C128C-MAPD-T require external pull-up resistors on SDA and SCL lines?

Yes, the AT24C128C-MAPD-T requires external pull-up resistors on both SDA and SCL lines because its SDA pin is open-drain and SCL is input-only. Microchip specifies maximum pull-up resistance of 10 kΩ, with 1.3 kΩ recommended for 400 kHz operation to meet rise-time requirements (tR ≤300 ns). The AT24C128C-MAPD-T will not function correctly without properly sized external pull-ups.

How does the Write-Protect (WP) pin function on the AT24C128C-MAPD-T?

The WP pin on the AT24C128C-MAPD-T is an active-high hardware lock: when tied to VCC, it inhibits all write operations to the entire memory array; when grounded, normal writes are enabled. If left floating, it defaults to GND via internal pull-down. This feature provides deterministic, power-fail-immune protection - unlike software-based locks, it remains effective during brown-out or reset conditions. The AT24C128C-MAPD-T pinout and WP behavior are detailed in Section 2.5 of the DS20006270B datasheet.

What is the memory organization of the AT24C128C-MAPD-T?

The AT24C128C-MAPD-T organizes its 128 Kbit (16,384 × 8) memory as 256 pages of 64 bytes each. This structure enables efficient page-write operations - up to 64 sequential bytes can be written in a single command with ≤5 ms internal write cycle time. Addressing uses a 14-bit word address transmitted after the device address byte. This layout is confirmed in Section 6 and Table 6-2 of the AT24C128C-MAPD-T datasheet DS20006270B.

Is the AT24C128C-MAPD-T compatible with 1.8 V I²C systems?

No, the AT24C128C-MAPD-T is not compatible with 1.8 V I²C systems. Its Grade 1 specification requires minimum VCC = 2.5 V, and its input thresholds (VIL ≤0.3×VCC, VIH ≥0.7×VCC) do not guarantee reliable logic recognition at 1.8 V supply. For 1.8 V operation, Microchip offers Grade 3 variants like AT24C128C-SSHM-T (1.7–5.5 V), but the AT24C128C-MAPD-T is strictly a 2.5–5.5 V Grade 1 part.

AT24C128C-MAPD-T Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 8-UFDFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 128Kbit

Memory Organization:: 16K x 8

Memory Interface:: I2C

Clock Frequency:: 400 kHz

Write Cycle Time - Word, Page:: 5ms

Access Time:: 900 ns

Voltage - Supply:: 2.5V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: 8-UDFN (2x3)

AT24C128C-MAPD-T FAQ

1.How can I place an order for AT24C128C-MAPD-T through Aetrix?

Please submit a Request for Quotation (RFQ) for AT24C128C-MAPD-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT24C128C-MAPD-T reliable?

The price and inventory of AT24C128C-MAPD-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C128C-MAPD-T is usually 5 days.

3.What payment methods are accepted for AT24C128C-MAPD-T?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C128C-MAPD-T transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT24C128C-MAPD-T?

AT24C128C-MAPD-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT24C128C-MAPD-T order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT24C128C-MAPD-T?

For technical support, including AT24C128C-MAPD-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C128C-MAPD-T requirements.

6.How does Aetrix verify that AT24C128C-MAPD-T is sourced from the original manufacturer or authorized distributors?

All AT24C128C-MAPD-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C128C-MAPD-T meets industry standards.

7.What is the process for return or replacement of AT24C128C-MAPD-T?

All AT24C128C-MAPD-T units undergo pre-shipment inspection (PSI). If there is an issue with AT24C128C-MAPD-T, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT24C128C-MAPD-T part is unused and in its original packaging.

Return procedure for AT24C128C-MAPD-T:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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