Microchip Technology AT24C128C-SSPD-T
- Part No.:
- AT24C128C-SSPD-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT24C128C-SSPD-T.pdf
- Description:
- IC EEPROM 128KBIT I2C 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT24C128C-SSPD-T from Microchip Technology is an AEC-Q100 Grade 1 automotive serial EEPROM with 128 Kbit (16,384 × 8) capacity, I²C-compatible two-wire interface operating at 100 kHz/400 kHz, 2.5V–5.5V supply, and -40°C to +125°C temperature range - deployed for configuration storage in engine control units, ADAS sensor modules, and body electronics.
For engineers reviewing the AT24C128C-SSPD-T datasheet, AT24C128C-SSPD-T pinout, AT24C128C-SSPD-T application, or AT24C128C-SSPD-T equivalent, key selection criteria include Grade 1 automotive qualification, 64-byte page write capability, hardware write-protection via WP pin, ultra-low standby current (≤6 μA), and SOIC-8 package compatibility with legacy board layouts.
Technical Context
The AT24C128C-SSPD-T implements a fully I²C-compliant slave interface with Schmitt-triggered, noise-filtered SDA/SCL inputs, supporting standard-mode (100 kHz) and fast-mode (400 kHz) timing. It uses internal high-voltage generation for EEPROM cell programming and features automatic address decoding across 14-bit memory space (0x0000–0x3FFF).
Its architecture includes a hardware write-protect circuit tied to the WP pin, internal pull-downs on A0/A1/A2 address pins (enabling up to eight devices per bus when hardwired), and power-on reset (POR) with 100 µs tPUP delay - ensuring deterministic initialization after VCC stabilization above 1.5 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16,384 × 8), organized as 256 pages × 64 bytes - enables efficient firmware parameter logging with partial-page writes. |
| Interface | I²C two-wire (SDA/SCL), 100 kHz / 400 kHz - compatible with microcontroller I²C peripherals without protocol translation. |
| Supply voltage | 2.5V to 5.5V (Grade 1) - supports direct connection to 3.3V or 5V automotive domains without level-shifting. |
| Operating temperature | -40°C to +125°C (AEC-Q100 Grade 1) - qualified for under-hood ECU deployment with full functionality at max junction temp. |
| Write endurance | 1,000,000 cycles - ensures >10 years of daily reconfiguration in telematics or calibration update scenarios. |
| Data retention | 100 years at 55°C - guarantees long-term integrity of safety-critical calibration data across vehicle lifetime. |
| Standby current | ≤6 μA at 5.0V - minimizes battery drain in always-on automotive modules during sleep mode. |
| Write cycle time | ≤5 ms per page - enables rapid nonvolatile save operations without blocking host CPU for extended periods. |
Pinout & Package
AT24C128C-SSPD-T is supplied in an 8-lead SOIC package (SSPD = SOIC narrow, 150 mil width), with gull-wing leads and RoHS-compliant matte tin plating. Pin 1 is marked by a beveled corner or dot; device orientation follows JEDEC MS-012.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Device address input | Hardwired to GND/VCC to set LSB of 7-bit I²C slave address (1010A2A1A0); floating = internally pulled down. |
| A1 | Device address input | Hardwired to GND/VCC to set middle bit of slave address; enables up to eight devices on same I²C bus. |
| A2 | Device address input | Hardwired to GND/VCC to set MSB of slave address bits; required for multi-device topology in ECUs. |
| GND | Ground reference | System ground return path; must be low-impedance to minimize noise coupling into SDA/SCL lines. |
| SDA | Serial data bidirectional I/O | Open-drain output/input; requires external 1.3 kΩ pull-up (400 kHz) and must be wire-OR'd with other I²C slaves. |
| SCL | Serial clock input | Input-only clock line; rising edge latches data, falling edge outputs data; must be pulled high externally. |
| WP | Hardware write-protect | Driven high to block all writes to entire memory array; driven low or floating for normal operation. |
| VCC | Power supply | 2.5V–5.5V input; slew rate ≤0.1 V/µs required; POR activates below 1.5 V threshold to prevent spurious writes. |
Key Features
| Feature | Design Value |
|---|---|
| Automotive qualification | AEC-Q100 Grade 1 certified - validated for reliability in harsh automotive environments including thermal cycling and vibration. |
| Noise-immune interface | Schmitt-trigger inputs + spike suppression filters on SDA/SCL - rejects >100 ns noise pulses common in 12V vehicle electrical systems. |
| Hardware data protection | Dedicated WP pin with internal pull-down - prevents accidental overwrites during power transients or firmware faults without software overhead. |
| Low-power operation | 3 mA max active current, 6 μA max standby current at 5V - extends battery life in always-on modules like gateway ECUs. |
| Page write flexibility | 64-byte page buffer with partial-page write support - allows atomic updates of sub-page data blocks without erasing full page. |
| Robust EEPROM cell | 1M write cycles / 100-year data retention - exceeds OEM requirements for infotainment settings, ADAS calibration, and emission control maps. |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
Use Scenario: Storing real-time calibration parameters (fuel trim, spark advance) and fault codes that persist across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile configuration storage slave on I²C bus, accessed during boot and runtime by MCU via polled or interrupt-driven transfers. Use Value: Enables zero-latency recall of adaptive learning values after cold start, meeting ISO 16750-2 transient immunity and -40°C to +125°C ambient requirements. |
Use Scenario: Retaining camera lens distortion coefficients, radar object detection thresholds, and sensor fusion weights across power cycles. IC Role / Device Role / Timing Role: Safety-relevant parameter store interfaced to ASIL-B microcontroller; WP pin tied to system security controller for write lockdown. Use Value: Guarantees integrity of ADAS calibration data under EMI-rich conditions (e.g., near inverters), supported by AEC-Q100 Grade 1 qualification. |
| Body Control Module (BCM) | Infotainment Head Unit |
Use Scenario: Saving user preferences (seat position, mirror angle, lighting profiles) and door lock configuration states. IC Role / Device Role / Timing Role: Low-power I²C EEPROM accessed during wake-up sequence; operates from 3.3V domain with <6 μA standby draw. Use Value: Eliminates need for backup battery or supercapacitor while maintaining state through 16-hour key-off period per ISO 16750-2. |
Use Scenario: Storing audio equalizer presets, Bluetooth pairing IDs, and display brightness history across firmware updates. IC Role / Device Role / Timing Role: Configuration memory mapped to I²C peripheral of application processor; supports 400 kHz fast-mode for responsive UI updates. Use Value: Ensures seamless user experience continuity after OTA updates, leveraging 5 ms max write cycle to avoid UI hang during save operations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M24C128-DFMN6TP/K | Same 128 Kbit I²C EEPROM, but AEC-Q100 Grade 2 (-40°C to +105°C); 1.7V–5.5V VCC range; SOIC-8 package. | Limited to under-dash applications (e.g., HVAC control), not qualified for under-hood use at +125°C. | Select when cost sensitivity outweighs Grade 1 requirement and ambient temperature stays ≤+105°C. |
| ON Semiconductor CAT24C128WI-GT3 | 128 Kbit I²C EEPROM, AEC-Q100 Grade 1, but only 1.7V–5.5V VCC; SOIC-8; 100 kHz max clock (no 400 kHz fast mode). | Not suitable for high-throughput parameter logging where 400 kHz bandwidth reduces MCU wait states. | Choose if design uses 1.7V–2.4V supply rails and does not require fast-mode timing compliance. |
Compared with ST M24C128-DFMN6TP/K and CAT24C128WI-GT3, the AT24C128C-SSPD-T uniquely combines Grade 1 temperature rating, 400 kHz fast-mode support, and 2.5V–5.5V operation - making it the only option qualified for high-speed, high-temperature ECU applications without voltage or timing compromise.
Availability
AT24C128C-SSPD-T is available at Aetrix Electronics and suitable for engine control units, ADAS sensor modules, and body control modules requiring stable component supply across automotive production lifecycles.
Supply support for AT24C128C-SSPD-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with global manufacturing and quality systems certified to IATF 16949.
The AT24C128C belongs to Microchip's automotive-grade serial EEPROM product line, designed specifically for reliable nonvolatile data storage in safety-critical and thermally demanding vehicle subsystems.
FAQ
What is the maximum I²C clock frequency supported by the AT24C128C-SSPD-T?
The AT24C128C-SSPD-T supports both standard-mode (100 kHz) and fast-mode (400 kHz) I²C operation. Its AC characteristics guarantee full timing compliance at 400 kHz with 1.3 kΩ pull-up resistors and 100 pF bus capacitance - enabling faster parameter reads/writes than legacy 100 kHz EEPROMs without sacrificing signal integrity.
Does the AT24C128C-SSPD-T require external pull-up resistors on SDA and SCL lines?
Yes, the AT24C128C-SSPD-T requires external pull-up resistors on both SDA and SCL. The datasheet specifies a maximum 1.3 kΩ value for 400 kHz operation with 100 pF bus load. SDA is open-drain and must be pulled high; SCL may be driven actively or pulled up. Omitting pull-ups will prevent I²C communication.
How is write protection implemented on the AT24C128C-SSPD-T?
Write protection on the AT24C128C-SSPD-T is controlled by the WP pin: when tied to VCC, the entire memory array is write-inhibited; when tied to GND or left floating (internally pulled down), normal write operations are enabled. This hardware-level lock operates independently of I²C commands and remains active during power transitions.
What package type does AT24C128C-SSPD-T use, and is it footprint-compatible with older AT24C128 variants?
The AT24C128C-SSPD-T uses an 8-lead SOIC package (SSPD = SOIC narrow, 150 mil width), identical in footprint and solder profile to legacy AT24C128B-SSPD-T and AT24C128N-SSHM-T. Pinout, dimensions, and thermal characteristics are fully compatible, enabling drop-in replacement in existing designs without PCB revision.
Is the AT24C128C-SSPD-T suitable for use in safety-critical automotive systems?
Yes - the AT24C128C-SSPD-T is AEC-Q100 Grade 1 qualified (-40°C to +125°C), has 1,000,000 write endurance and 100-year data retention, and includes POR, WP pin, and noise-suppressed I²C interface - all verified for functional safety relevance in ASIL-B systems per ISO 26262 guidelines when integrated with appropriate system-level diagnostics.
AT24C128C-SSPD-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT24C128C-SSPD-T FAQ
1.How can I place an order for AT24C128C-SSPD-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C128C-SSPD-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C128C-SSPD-T reliable?
The price and inventory of AT24C128C-SSPD-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C128C-SSPD-T is usually 5 days.
3.What payment methods are accepted for AT24C128C-SSPD-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C128C-SSPD-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C128C-SSPD-T?
AT24C128C-SSPD-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C128C-SSPD-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C128C-SSPD-T?
For technical support, including AT24C128C-SSPD-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C128C-SSPD-T requirements.
6.How does Aetrix verify that AT24C128C-SSPD-T is sourced from the original manufacturer or authorized distributors?
All AT24C128C-SSPD-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C128C-SSPD-T meets industry standards.
7.What is the process for return or replacement of AT24C128C-SSPD-T?
All AT24C128C-SSPD-T units undergo pre-shipment inspection (PSI). If there is an issue with AT24C128C-SSPD-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C128C-SSPD-T part is unused and in its original packaging.
Return procedure for AT24C128C-SSPD-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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