Microchip Technology AT24C128N-10SI-2.7
- Part No.:
- AT24C128N-10SI-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT24C128N-10SI-2.7.pdf
- Description:
- IC EEPROM 128KBIT I2C 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,698
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT24C128N-10SI-2.7 from Microchip Technology (formerly Atmel) is a 128 Kbit (16,384 × 8) two-wire serial EEPROM with low-voltage operation (2.7V to 5.5V), 400 kHz I²C bus compatibility at 2.7V, and industrial temperature range (−40°C to +85°C). It features hardware write protection via the WP pin, 64-byte page write capability, and 100,000 write cycles endurance - deployed in embedded systems requiring nonvolatile parameter storage under constrained power and space.
For engineers reviewing the AT24C128N-10SI-2.7 datasheet, AT24C128N-10SI-2.7 pinout, AT24C128N-10SI-2.7 application, or AT24C128N-10SI-2.7 equivalent, key selection criteria include VCC operating range (2.7–5.5 V), I²C clock frequency (400 kHz max at 2.7 V), industrial-grade temperature rating, 8-pin SOIC package (8S1), and hardware/software write protection implementation using the WP pin.
Technical Context
The AT24C128N-10SI-2.7 implements a standard I²C-compatible two-wire interface with open-drain SDA and Schmitt-triggered SCL inputs for noise immunity. Its internal address counter supports current-address, random-address, and sequential read modes, while page-write logic enables burst writes up to 64 bytes without rollover across pages.
Device addressing uses A0 and A1 pins to support up to four devices on a shared bus; unconnected pins default to logic low. Write protection is enforced by tying WP high (VCC) to inhibit all writes, or leaving it floating (internally pulled down) for normal operation - enabling both hardware and software-controlled data security.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16,384 × 8), sufficient for firmware configuration tables or calibration data in microcontroller-based systems |
| Supply voltage | 2.7 V to 5.5 V - supports mixed-voltage designs including 3.3 V and 5 V systems without level shifting |
| I²C speed | 400 kHz maximum at 2.7 V - enables fast parameter updates while maintaining robustness in noisy industrial environments |
| Write endurance | 100,000 cycles - ensures reliable logging or field-updatable settings over multi-year product lifetimes |
| Data retention | 40 years at 85°C - guarantees long-term integrity of stored calibration, serial numbers, or security keys |
| Operating temperature | −40°C to +85°C - qualified for industrial control, automotive body electronics, and outdoor IoT edge nodes |
| Page size | 64 bytes - optimizes write efficiency for block-oriented data such as sensor calibration matrices or network credentials |
Pinout & Package
AT24C128N-10SI-2.7 is housed in an 8-pin JEDEC SOIC package (8S1), 0.150" wide, with standard gull-wing leads and 1.27 mm pitch. Pin 1 is marked by a notch or dot; device orientation follows JEDEC MS-012AA.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Device address input | Hardwired low/high or left floating (default low) to configure one of four possible I²C addresses on shared bus |
| A1 | Device address input | Same function as A0; together with A0, selects device address (0x50–0x53) per I²C specification |
| NC | No-connect terminal | Internally unused; must remain unconnected - no external tie required |
| GND | Ground reference | Return path for VCC and signal logic; requires low-impedance connection to system ground plane |
| VCC | Power supply | Accepts 2.7–5.5 V; bypass capacitor (0.1 µF ceramic) recommended near pin for noise suppression |
| WP | Write protect control | Pulled high to VCC to disable all writes; floating or grounded enables full read/write access |
| SCL | Serial clock input | Positive-edge sampled clock; requires external pull-up resistor (typically 2.2–10 kΩ) to VCC |
| SDA | Serial data I/O | Open-drain bidirectional line; shares pull-up with SCL or uses dedicated resistor; supports wire-OR with other I²C devices |
Key Features
| Feature | Design Value |
|---|---|
| Low-voltage operation | Functional down to 2.7 V - eliminates need for voltage regulators in 3.3 V systems and extends battery life in portable devices |
| Hardware write protection | WP pin directly disables write commands at silicon level - prevents accidental or malicious overwrites during power transitions or firmware faults |
| 64-byte page write mode | Reduces write transaction overhead by up to 63× vs. byte writes - critical for time-sensitive calibration updates in real-time control loops |
| Schmitt-trigger inputs | Filters noise on SCL/SDA lines without external components - improves reliability in electrically harsh environments (e.g., motor drives, factory automation) |
| 100,000 write cycles | Enables daily reconfiguration over 270+ years - suitable for field-programmable devices requiring frequent firmware patching or user customization |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
Use Scenario: Storing factory-calibrated gain/offset coefficients and temperature compensation curves for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile parameter storage accessed via I²C during boot or recalibration; retains values across power cycles and thermal stress. Use Value: Eliminates need for external trimming potentiometers or laser calibration; enables post-manufacture field recalibration without hardware modification. | Use Scenario: Holding patient-specific therapy parameters, device serial number, and regulatory compliance flags in portable infusion pumps. IC Role / Device Role / Timing Role: Secure, tamper-resistant memory for safety-critical configuration data; WP pin tied to system security controller to lock settings after initialization. Use Value: Meets IEC 62304 Class C software requirements for data integrity; supports audit trails and version-controlled firmware updates. |
| Automotive Body Control Module | Smart Energy Metering |
Use Scenario: Recording door lock/unlock history, mirror position presets, and lighting profiles in vehicle BCMs operating across −40°C to +85°C ambient. IC Role / Device Role / Timing Role: Industrial-grade EEPROM interfaced to 8-bit/16-bit MCU over I²C; withstands automotive load dump and cold-crank conditions via robust VCC tolerance. Use Value: Survives 15-year vehicle lifecycle without data corruption; supports OTA personalization features without requiring MCU flash wear leveling. | Use Scenario: Storing tariff schedules, meter calibration constants, and tamper-detection logs in ANSI C12.22-compliant smart electricity meters. IC Role / Device Role / Timing Role: Long-retention memory for revenue-grade data; WP pin controlled by metrology ASIC to prevent unauthorized parameter changes. Use Value: 40-year data retention meets ANSI C12.19 archival requirements; page-write mode accelerates time-of-use schedule uploads during utility maintenance windows. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C128B-SSHM-T | Same 128 Kbit density and 2.7–5.5 V range, but in 8-lead TSSOP (14T) package; slightly higher standby current (0.6 µA vs. 0.5 µA at 2.7 V) | TSSOP offers better thermal dissipation and smaller footprint than SOIC; preferred for high-density PCB layouts | Select when board space is constrained and thermal performance is prioritized over legacy SOIC compatibility |
| BR24G128FJ-WE2 | Rohm part with identical 128 Kbit capacity and 2.7–5.5 V operation, but rated for −40°C to +105°C; supports 1 MHz I²C at 5 V only | Broadened temperature range suits under-hood automotive use; lacks 400 kHz guarantee at 2.7 V - verify timing margins in low-VCC designs | Choose for extended temperature applications where 2.7 V operation at 400 kHz is not required |
Compared with AT24C128B-SSHM-T and BR24G128FJ-WE2, the AT24C128N-10SI-2.7 delivers guaranteed 400 kHz I²C performance at 2.7 V in a widely supported 8-pin SOIC package, making it optimal for industrial and medical systems needing proven interoperability, moderate board area, and strict low-voltage timing compliance.
Availability
AT24C128N-10SI-2.7 is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, and automotive body control modules requiring stable component supply across extended temperature ranges and multi-year production cycles.
Supply support for AT24C128N-10SI-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions, with broad industrial and automotive qualification coverage.
The AT24C128N-10SI-2.7 belongs to Microchip's AT24C serial EEPROM product line, designed specifically for reliable, low-power, I²C-based parameter storage in space- and power-constrained embedded systems.
FAQ
What is the maximum I²C clock frequency supported by AT24C128N-10SI-2.7 at 2.7 V?
The AT24C128N-10SI-2.7 supports up to 400 kHz I²C clock frequency when operated at 2.7 V, as specified in its AC characteristics table. This is lower than the 1 MHz maximum achievable at 5 V, reflecting timing margin adjustments for reduced supply voltage - critical for ensuring reliable communication in 3.3 V industrial systems where noise margins are tighter.
How does the WP pin function on AT24C128N-10SI-2.7?
The WP (Write Protect) pin on AT24C128N-10SI-2.7 provides hardware-level write inhibition: when tied to VCC, all write operations (byte and page) are blocked; when grounded or left floating (internally pulled down), full read/write access is enabled. This dual-mode behavior allows both permanent protection (hardwired VCC) and dynamic control (MCU-driven logic level), enhancing security in safety-critical AT24C128N-10SI-2.7 deployments.
What package type is used for AT24C128N-10SI-2.7?
AT24C128N-10SI-2.7 uses an 8-pin JEDEC SOIC package (designated 8S1), 0.150" wide, with gull-wing leads and 1.27 mm pitch. This industry-standard package ensures compatibility with automated assembly processes and widely available socketing solutions, simplifying prototyping and high-volume manufacturing of AT24C128N-10SI-2.7-based designs.
Can AT24C128N-10SI-2.7 be used alongside other AT24C devices on the same I²C bus?
Yes - AT24C128N-10SI-2.7 supports cascading up to four devices on a single I²C bus using its A0 and A1 address pins. These pins configure the device's 3-bit I²C address (bits 4–2), allowing unique addressing within the 0x50–0x53 range. This capability enables modular system design where multiple AT24C128N-10SI-2.7 units store distinct subsystem parameters without bus contention.
What is the data retention period for AT24C128N-10SI-2.7 at 85°C?
AT24C128N-10SI-2.7 guarantees 40 years of data retention at +85°C, as confirmed in its DC characteristics table. This specification reflects worst-case accelerated testing and ensures long-term integrity of stored calibration data, serial numbers, or security keys in thermally stressed environments - a key requirement for AT24C128N-10SI-2.7 applications in industrial and automotive systems.
AT24C128N-10SI-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 550 ns
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT24C128N-10SI-2.7 FAQ
1.How can I place an order for AT24C128N-10SI-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C128N-10SI-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C128N-10SI-2.7 reliable?
The price and inventory of AT24C128N-10SI-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C128N-10SI-2.7 is usually 5 days.
3.What payment methods are accepted for AT24C128N-10SI-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C128N-10SI-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C128N-10SI-2.7?
AT24C128N-10SI-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C128N-10SI-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C128N-10SI-2.7?
For technical support, including AT24C128N-10SI-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C128N-10SI-2.7 requirements.
6.How does Aetrix verify that AT24C128N-10SI-2.7 is sourced from the original manufacturer or authorized distributors?
All AT24C128N-10SI-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C128N-10SI-2.7 meets industry standards.
7.What is the process for return or replacement of AT24C128N-10SI-2.7?
All AT24C128N-10SI-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT24C128N-10SI-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C128N-10SI-2.7 part is unused and in its original packaging.
Return procedure for AT24C128N-10SI-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT24C128N-10SI-2.7 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
