Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

Microchip Technology AT24C64D-MAPD-E

Name: AT24C64D-MAPD-E
Brand: Microchip Technology
SKU: AT24C64D-MAPD-E
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: AT24C64D-MAPD-E

Manufacturer:: Microchip Technology

Category:: Memory

Package:: 8-UFDFN Exposed Pad

Datasheet:: AT24C64D-MAPD-E.pdf

Description:: IC EEPROM 64KBIT I2C 8UDFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,959

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

AT24C64D-MAPD-E from Microchip Technology is a 64-Kbit (8,192 × 8) I²C-compatible automotive-grade serial EEPROM with AEC-Q100 Grade 1 qualification (-40°C to +125°C), 1.7V–5.5V supply range, and hardware write-protection via WP pin. It delivers ultra-low standby current (≤6 μA), supports 400 kHz Fast-mode I²C, and enables partial page writes in 32-byte pages for robust configuration storage in engine control units.

For engineers reviewing the AT24C64D-MAPD-E datasheet, AT24C64D-MAPD-E pinout, AT24C64D-MAPD-E application, or AT24C64D-MAPD-E equivalent, key selection criteria include automotive temperature compliance, I²C bus noise immunity (Schmitt-trigger inputs), page-write timing (≤5 ms), endurance (1M cycles), and package-specific pin mapping for SOIC-8 footprint compatibility.

Technical Context

The AT24C64D-MAPD-E operates as an I²C slave device with fixed 7-bit device address prefix 1010b and three hardware-configurable address bits (A0–A2), enabling up to eight devices on one bus. Its internal architecture uses row/column decoding of a 256-page × 32-byte memory array, with automatic address incrementing during sequential reads.

Communication relies on open-drain SDA/SCL with integrated Schmitt triggers and spike suppression filters; data is latched on SCL rising edge and output on falling edge. Write protection is implemented via dedicated WP pin-tied to VCC to inhibit all writes, or GND for full write access-without requiring software locks.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory size	64 Kbit (8,192 × 8 bits), organized as 256 pages × 32 bytes - enables efficient firmware parameter storage with page-level granularity.
Supply voltage	1.7V to 5.5V - supports wide-input automotive power rails including 3.3V and 5V systems without level-shifting.
Operating temperature	-40°C to +125°C (AEC-Q100 Grade 1) - qualified for under-hood ECU and transmission control applications.
I²C speed modes	Standard mode (100 kHz) and Fast mode (400 kHz) - ensures compatibility with legacy and high-throughput microcontrollers.
Write endurance	1,000,000 write cycles - guarantees long-term reliability in dynamic calibration or logging use cases.
Data retention	100 years at 55°C - meets automotive lifetime requirements for nonvolatile configuration data.
Standby current	≤6 μA at 5.0V - minimizes quiescent power draw in always-on vehicle modules.
Write cycle time	≤5 ms maximum - enables rapid parameter updates without blocking host CPU for extended periods.

Pinout & Package

AT24C64D-MAPD-E is supplied in an 8-lead SOIC package (3.9 mm × 4.9 mm body, 1.27 mm pitch), pin-compatible with industry-standard I²C EEPROM footprints. The package includes gull-wing leads and RoHS-compliant matte tin plating.

Pin/Terminal	Circuit Role	Design Meaning
A0	Device address input	Hardwired to GND or VCC to configure 1 of 8 possible I²C addresses; internally pulled down if floating - requires explicit biasing for deterministic addressing.
A1	Device address input	Second hardware address bit; used with A0/A2 to select unique slave address on shared I²C bus - critical for multi-EEPROM system designs.
A2	Device address input	Third hardware address bit; completes 3-bit address field (A2–A0) - enables daisy-chained configuration storage across multiple ECUs.
GND	Ground reference	System return path for VCC and signal logic; must be low-impedance connection to avoid noise coupling into SDA/SCL lines.
SDA	Serial data bidirectional I/O	Open-drain line requiring external pull-up resistor (≤10 kΩ); transmits/receives command/data/ACK/NACK - shared across all I²C slaves on bus.
SCL	Serial clock input	Master-generated clock controlling data timing; rising edge latches input, falling edge outputs data - must be pulled high when idle.
WP	Hardware write-protect	Active-high pin: tied to VCC blocks all writes to entire memory array; tied to GND enables full read/write access - provides fail-safe data integrity.
VCC	Power supply	1.7V–5.5V operation; slew rate ≤0.1 V/µs required during power-up to ensure reliable POR behavior and prevent spurious writes.

Key Features

Feature	Design Value
Automotive AEC-Q100 Grade 1 qualification	Validated for -40°C to +125°C operation with full electrical characterization - eliminates need for additional thermal derating in engine bay deployments.
32-byte page write with partial write support	Allows writing 1–32 bytes per transaction without erasing adjacent bytes - reduces wear and improves update efficiency for sparse parameter sets.
Schmitt-trigger inputs with noise filtering	Suppresses bus noise up to 50 ns spikes on SDA/SCL - enhances reliability in electrically noisy automotive environments (e.g., near ignition systems).
Ultra-low standby current (≤6 μA)	Minimizes battery drain in always-on modules such as body control units - extends vehicle sleep-mode duration without compromising data retention.
Dedicated hardware WP pin	Enables irreversible write lock during critical operations (e.g., firmware boot) - prevents accidental overwrites without software intervention or MCU involvement.
100-year data retention at 55°C	Guarantees configuration persistence over full vehicle service life - satisfies OEM requirements for zero-maintenance nonvolatile storage.

Applications

Engine Control Unit (ECU)	Advanced Driver Assistance Systems (ADAS)
Use Scenario: Storing adaptive fuel trim tables, knock sensor calibration offsets, and cold-start enrichment parameters that must survive ignition cycles and thermal cycling. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing persistent memory mapped via I²C for real-time MCU access during engine runtime. Use Value: Enables self-learning engine behavior while maintaining AEC-Q100 compliance and 100-year data retention under under-hood thermal stress.	Use Scenario: Holding camera lens calibration coefficients, radar beamforming profiles, and sensor fusion metadata updated during factory programming or OTA updates. IC Role / Device Role / Timing Role: Secure, write-protected configuration store accessed during ADAS module power-up to initialize vision/radar subsystems. Use Value: Hardware WP pin prevents runtime corruption of safety-critical calibration data; 400 kHz I²C enables fast loading before sensor activation.
Transmission Control Module (TCM)	Body Control Module (BCM)
Use Scenario: Retaining gear shift adaptation maps, clutch wear compensation values, and fault history logs across power loss events in automatic transmissions. IC Role / Device Role / Timing Role: High-endurance EEPROM interfacing directly with TCM's main MCU over I²C for cyclic parameter updates during drive cycles. Use Value: 1M write cycles withstand frequent recalibration events; 5 ms max write time avoids interrupt latency issues during real-time torque management.	Use Scenario: Saving user preferences (window positions, mirror angles, lighting themes) and door-lock configuration states that persist through battery disconnects. IC Role / Device Role / Timing Role: Low-power serial memory operating in BCM's always-on domain, waking only during I²C transactions to minimize parasitic drain. Use Value: 6 μA standby current extends vehicle quiescent current budget; SOIC-8 package simplifies layout in space-constrained BCM PCBs.

Engine Control Unit (ECU)

Advanced Driver Assistance Systems (ADAS)

Use Scenario: Storing adaptive fuel trim tables, knock sensor calibration offsets, and cold-start enrichment parameters that must survive ignition cycles and thermal cycling.

IC Role / Device Role / Timing Role: Nonvolatile configuration register providing persistent memory mapped via I²C for real-time MCU access during engine runtime.

Use Value: Enables self-learning engine behavior while maintaining AEC-Q100 compliance and 100-year data retention under under-hood thermal stress.

Use Scenario: Holding camera lens calibration coefficients, radar beamforming profiles, and sensor fusion metadata updated during factory programming or OTA updates.

IC Role / Device Role / Timing Role: Secure, write-protected configuration store accessed during ADAS module power-up to initialize vision/radar subsystems.

Use Value: Hardware WP pin prevents runtime corruption of safety-critical calibration data; 400 kHz I²C enables fast loading before sensor activation.

Transmission Control Module (TCM)

Body Control Module (BCM)

Use Scenario: Retaining gear shift adaptation maps, clutch wear compensation values, and fault history logs across power loss events in automatic transmissions.

IC Role / Device Role / Timing Role: High-endurance EEPROM interfacing directly with TCM's main MCU over I²C for cyclic parameter updates during drive cycles.

Use Value: 1M write cycles withstand frequent recalibration events; 5 ms max write time avoids interrupt latency issues during real-time torque management.

Use Scenario: Saving user preferences (window positions, mirror angles, lighting themes) and door-lock configuration states that persist through battery disconnects.

IC Role / Device Role / Timing Role: Low-power serial memory operating in BCM's always-on domain, waking only during I²C transactions to minimize parasitic drain.

Use Value: 6 μA standby current extends vehicle quiescent current budget; SOIC-8 package simplifies layout in space-constrained BCM PCBs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
STMicroelectronics M24C64-RMN6TP	Same 64-Kbit capacity, AEC-Q100 Grade 2 (-40°C to +105°C), but lacks Grade 1 qualification and has higher 10 μA standby current.	Not suitable for under-hood locations exceeding +105°C; acceptable for cabin-mounted modules like HVAC controllers.	Select when Grade 2 temperature range suffices and ST ecosystem alignment is preferred.
ON Semiconductor CAT24C64WI-GT3	64-Kbit, AEC-Q100 Grade 1, but rated for 400 kHz only (no 100 kHz backward compatibility) and offers no WP pin - write protection requires software-only implementation.	Requires MCU firmware changes to emulate hardware write lock; unsuitable where fail-safe hardware protection is mandated.	Choose only if I²C bus operates exclusively at 400 kHz and software-controlled protection is acceptable per system safety analysis.

Compared with M24C64-RMN6TP and CAT24C64WI-GT3, AT24C64D-MAPD-E uniquely combines full AEC-Q100 Grade 1 compliance, hardware WP pin, dual-speed I²C support, and sub-6 μA standby current - making it the only option qualified for high-reliability under-hood storage with deterministic write inhibition.

Availability

AT24C64D-MAPD-E is available at Aetrix Electronics and suitable for engine control units, ADAS camera modules, transmission control systems, and body control modules requiring stable component supply across automotive production lifecycles.

Supply support for AT24C64D-MAPD-E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with ISO/TS 16949-certified automotive manufacturing processes.

The AT24C64D-MAPD-E belongs to Microchip's automotive-qualified serial EEPROM product line, engineered specifically for mission-critical nonvolatile storage in harsh-temperature vehicle subsystems where data integrity and long-term reliability are mandatory.

FAQ

What is the maximum I²C clock frequency supported by the AT24C64D-MAPD-E?

The AT24C64D-MAPD-E supports both Standard mode (100 kHz) and Fast mode (400 kHz) I²C operation. Its AC characteristics guarantee reliable communication up to 400 kHz with tLOW ≥1200 ns and tHIGH ≥600 ns at VCC = 1.7V–5.5V. This dual-speed capability ensures interoperability with legacy and modern microcontrollers without protocol translation.

Does the AT24C64D-MAPD-E require external pull-up resistors on SDA and SCL lines?

Yes, the AT24C64D-MAPD-E requires external pull-up resistors on both SDA and SCL lines because these pins are open-drain. Microchip specifies a maximum value of 10 kΩ for the pull-up resistor; typical designs use 2.2 kΩ to 4.7 kΩ to meet rise-time requirements (tR ≤300 ns at 400 kHz). Failure to install pull-ups will prevent I²C communication.

How does the write-protect (WP) pin function on the AT24C64D-MAPD-E?

The WP pin on the AT24C64D-MAPD-E is an active-high hardware lock: when tied to VCC, it inhibits all write operations to the entire 64-Kbit memory array; when tied to GND, normal read/write access is enabled. If left floating, it defaults to GND via internal pull-down, but Microchip recommends explicit biasing to avoid noise-induced state transitions in automotive environments.

What is the memory organization of the AT24C64D-MAPD-E?

The AT24C64D-MAPD-E organizes its 64 Kbit as 8,192 words of 8 bits each, segmented into 256 pages of 32 bytes. This structure enables efficient page writes (1–32 bytes per transaction) and supports random, current-address, and sequential read modes. Addressing uses a 13-bit word address transmitted after the 7-bit device address byte.

Is the AT24C64D-MAPD-E compatible with standard SOIC-8 PCB footprints?

Yes, the AT24C64D-MAPD-E uses an industry-standard 8-lead SOIC package (3.9 mm × 4.9 mm body, 1.27 mm lead pitch) fully compatible with IPC-7351B SOIC-8 land patterns. Pin 1 is marked with a beveled corner, and the pinout matches JEDEC MS-012 - enabling drop-in replacement in existing designs using other SOIC-8 I²C EEPROMs.

AT24C64D-MAPD-E Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 8-UFDFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 64Kbit

Memory Organization:: 8K x 8

Memory Interface:: I2C

Clock Frequency:: 400 kHz

Write Cycle Time - Word, Page:: 5ms

Access Time:: 900 ns

Voltage - Supply:: 2.5V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: 8-UDFN (2x3)

AT24C64D-MAPD-E FAQ

1.How can I place an order for AT24C64D-MAPD-E through Aetrix?

Please submit a Request for Quotation (RFQ) for AT24C64D-MAPD-E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT24C64D-MAPD-E reliable?

The price and inventory of AT24C64D-MAPD-E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C64D-MAPD-E is usually 5 days.

3.What payment methods are accepted for AT24C64D-MAPD-E?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C64D-MAPD-E transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT24C64D-MAPD-E?

AT24C64D-MAPD-E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT24C64D-MAPD-E order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT24C64D-MAPD-E?

For technical support, including AT24C64D-MAPD-E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C64D-MAPD-E requirements.

6.How does Aetrix verify that AT24C64D-MAPD-E is sourced from the original manufacturer or authorized distributors?

All AT24C64D-MAPD-E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C64D-MAPD-E meets industry standards.

7.What is the process for return or replacement of AT24C64D-MAPD-E?

All AT24C64D-MAPD-E units undergo pre-shipment inspection (PSI). If there is an issue with AT24C64D-MAPD-E, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT24C64D-MAPD-E part is unused and in its original packaging.

Return procedure for AT24C64D-MAPD-E:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…