Microchip Technology AT24C64D-XHM-T
- Part No.:
- AT24C64D-XHM-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT24C64D-XHM-T.pdf
- Description:
- IC EEPROM 64KBIT I2C 1MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT24C64D-XHM-T from Microchip Technology is a 64-Kbit I²C-compatible serial EEPROM organized as 8,192 × 8 bits, operating from 1.7V to 5.5V with industrial temperature range (−40°C to +85°C), 1 MHz Fast Mode Plus support at ≥2.5V, and hardware write-protection via dedicated WP pin - used for nonvolatile configuration storage in embedded controllers and sensor modules.
For engineers reviewing the AT24C64D-XHM-T datasheet, AT24C64D-XHM-T pinout, AT24C64D-XHM-T application, or AT24C64D-XHM-T equivalent, key selection considerations include I²C bus voltage compatibility (1.7–5.5V), page-write capability (32-byte pages), ultra-low standby current (≤6 µA), and 8-lead XDFN package footprint with exposed pad.
Technical Context
The AT24C64D-XHM-T implements a two-wire I²C interface with Schmitt-triggered, noise-filtered SDA/SCL inputs and supports Standard (100 kHz), Fast (400 kHz), and Fast Mode Plus (1 MHz) clock rates depending on VCC level. Its memory array is segmented into 256 pages of 32 bytes each, enabling partial-page writes without erasing adjacent data.
It features an internal power-on reset (POR) circuit with VPOR threshold ≤1.5 V and tPUP delay ≥100 µs, plus hardware address inputs (A0–A2) allowing up to eight devices on one bus. Write protection is controlled solely by the WP pin state - tied to VCC for full-array lockout, GND for normal operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 64 Kbit (8,192 × 8), sufficient for firmware calibration tables or device identity storage |
| Supply voltage | 1.7V to 5.5V - enables direct interfacing with 1.8V, 3.3V, and 5V microcontrollers without level shifters |
| I²C speed modes | 100 kHz (1.7–5.5V), 400 kHz (1.7–5.5V), 1 MHz (2.5–5.5V) - supports high-throughput updates in powered systems |
| Write endurance | 1,000,000 cycles - suitable for logging or counter applications with frequent updates |
| Data retention | 100 years at 55°C - ensures long-term reliability in unattended industrial deployments |
| Standby current | ≤6 µA at 5.0V - minimizes battery drain in always-on IoT edge nodes |
| Page write size | 32 bytes - allows efficient burst writes while avoiding overwriting unrelated configuration fields |
Pinout & Package
AT24C64D-XHM-T is packaged in an 8-pad XDFN (0.4 mm pitch, 2.0 × 1.6 mm body) with exposed thermal pad (recommended to be connected to GND). Pin numbering follows standard top-view orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Hardware device address input | Configures LSB of 7-bit I²C slave address; pulled down internally if floating - must be hard-wired for deterministic multi-device bus addressing |
| A1 | Hardware device address input | Configures middle bit of 7-bit I²C slave address; enables up to eight unique addresses (1010xxxR/W) on shared bus |
| A2 | Hardware device address input | Configures MSB of hardware address; combined with A0/A1, defines full 3-bit address extension beyond fixed 1010 prefix |
| GND | Power reference ground | Return path for VCC and all I/O; exposed pad should be soldered to PCB ground plane for thermal and EMI performance |
| SDA | Open-drain bidirectional data line | Requires external pull-up resistor (≤10 kΩ); shares bus with other open-drain devices; latched on SCL rising edge |
| SCL | Input clock line | Drives timing for all transfers; must be pulled high externally; falling edge clocks data out, rising edge latches data in |
| WP | Hardware write-protection control | Logic high (VCC) disables all writes to entire memory array; logic low (GND) enables write operations - no software lock required |
| VCC | Power supply input | Supplies core and I/O circuitry; must ramp monotonically at ≤0.1 V/µs; stable ≥100 µs before first command after power-up |
Key Features
| Feature | Design Value |
|---|---|
| Fast Mode Plus support | 1 MHz I²C operation at 2.5–5.5V enables 2.5× faster writes vs. standard mode - critical for field firmware patching |
| 32-byte page write | Allows partial writes within 32-byte boundaries without erasing adjacent bytes - preserves integrity of mixed-parameter sectors |
| Schmitt-triggered inputs | Filters bus noise and rejects transients <100 ns (Fast Mode) or <50 ns (FM+) - improves robustness in electrically noisy industrial cabinets |
| Internal address pull-downs | A0–A2 and WP pins default to GND when unconnected - prevents undefined behavior during prototyping or incomplete routing |
| Green packaging | Lead-free, halide-free, RoHS-compliant XDFN package meets global environmental compliance requirements for CE, FCC, and REACH |
Applications
| Industrial Sensor Calibration | Smart Meter Firmware Storage |
|---|---|
Use Scenario: Storing factory-trimmed gain/offset coefficients and temperature compensation curves in pressure or flow sensors deployed in HVAC or process control systems. IC Role / Device Role / Timing Role: Nonvolatile configuration register holding calibrated parameters accessed at power-on by MCU ADC driver firmware. Use Value: Eliminates need for external trimming components; enables field recalibration via I²C without reprogramming MCU flash. | Use Scenario: Retaining tariff schedules, billing counters, and communication module credentials in utility-grade electricity meters operating for >15 years. IC Role / Device Role / Timing Role: Secure, long-life parameter vault with hardware write-lock (WP tied to secure domain) preventing unauthorized firmware or rate table modification. Use Value: Meets ANSI C12.1 and IEC 62056 requirements for tamper-resistant, 100-year data retention under thermal cycling. |
| IoT Edge Node Identity | PLC Configuration Backup |
Use Scenario: Holding unique device identifiers (MAC, serial number), TLS certificate fingerprints, and OTA update metadata in battery-powered wireless gateways. IC Role / Device Role / Timing Role: Low-power persistent ID store accessed only during boot or secure provisioning - draws ≤6 µA in standby. Use Value: Enables zero-touch enrollment in cloud platforms without requiring MCU to retain identity in volatile RAM or larger flash. | Use Scenario: Saving ladder logic runtime variables, I/O mapping, and alarm history across power cycles in DIN-rail programmable logic controllers. IC Role / Device Role / Timing Role: Real-time backup memory updated asynchronously via I²C during idle scan cycles - survives brownouts and emergency stops. Use Value: Prevents loss of operational state during unscheduled shutdowns; supports deterministic restart without manual reconfiguration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M24C64-WMN6TP | Same 64-Kbit density and I²C interface, but rated for −40°C to +105°C and uses SO8 package; lacks FM+ (1 MHz) support - max 400 kHz at 1.7–5.5V | Better suited for under-hood automotive ECUs requiring extended temperature range, but slower write throughput | Select M24C64-WMN6TP only if ambient exceeds +85°C and 1 MHz writes are unnecessary |
| BR24G64FJ-3GE2 | 64-Kbit I²C EEPROM with identical 1.7–5.5V range and 1 MHz FM+ support, but in 8-pin TSSOP; includes software write-protection in addition to hardware WP pin | Offers dual-layer protection (HW + SW) for safety-critical firmware flags, but requires additional I²C command overhead | Choose BR24G64FJ-3GE2 when regulatory certification demands redundant write-lock mechanisms beyond single-pin hardware control |
Compared with M24C64-WMN6TP and BR24G64FJ-3GE2, the AT24C64D-XHM-T delivers optimal balance of industrial temperature compliance, 1 MHz write speed, and minimal board area via XDFN - making it preferred for space-constrained, high-throughput embedded designs where extended temp or dual-locking aren't mandatory.
Availability
AT24C64D-XHM-T is available at Aetrix Electronics and suitable for industrial sensor calibration, smart meter firmware storage, and IoT edge node identity management requiring stable component supply across multi-year production cycles.
Supply support for AT24C64D-XHM-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with ISO 9001-certified manufacturing and global distribution.
The AT24C64D belongs to Microchip's legacy serial EEPROM product line, designed specifically for reliable, low-voltage nonvolatile storage in cost-sensitive industrial and consumer electronics where I²C simplicity and proven endurance are prioritized over advanced features like SPI or Quad I/O.
FAQ
What is the maximum I²C clock frequency supported by the AT24C64D-XHM-T?
The AT24C64D-XHM-T supports 100 kHz (Standard Mode), 400 kHz (Fast Mode), and 1 MHz (Fast Mode Plus) I²C clock frequencies. The 1 MHz mode requires VCC ≥2.5V; below that, maximum speed is 400 kHz across 1.7–5.5V. This enables faster firmware updates in powered systems while maintaining compatibility with legacy 100 kHz controllers.
Does the AT24C64D-XHM-T require external pull-up resistors on SDA and SCL lines?
Yes, the AT24C64D-XHM-T requires external pull-up resistors on both SDA and SCL lines because its SDA pin is open-drain and SCL is an input-only pin. Microchip specifies maximum values of 10 kΩ for SDA and recommends ≤10 kΩ for SCL; typical values are 4.7 kΩ for 400 kHz and 1.3 kΩ for 1 MHz operation to meet rise-time requirements.
How does the write-protect (WP) pin function on the AT24C64D-XHM-T?
The WP pin on the AT24C64D-XHM-T provides hardware-level write inhibition: when tied to VCC, it blocks all write operations to the entire 64-Kbit memory array; when tied to GND, normal writes are enabled. If left floating, WP defaults to GND due to internal pull-down, but Microchip recommends hard-wiring it to avoid noise-induced glitches in industrial environments.
What is the memory organization and page structure of the AT24C64D-XHM-T?
The AT24C64D-XHM-T organizes its 64-Kbit capacity as 8,192 words × 8 bits, divided into 256 pages of 32 bytes each. This structure enables efficient 32-byte page writes - allowing partial writes within a page without disturbing adjacent bytes - and supports random and sequential read modes with no page boundary restrictions.
Is the AT24C64D-XHM-T compatible with 1.8V I²C systems?
Yes, the AT24C64D-XHM-T is fully compatible with 1.8V I²C systems: it operates from 1.7V to 5.5V, supports 100 kHz and 400 kHz modes across that full range, and meets I²C bus voltage thresholds (VIH ≥0.7×VCC, VIL ≤0.3×VCC) at 1.8V. No level translation is needed when interfacing with 1.8V microcontrollers or FPGAs.
AT24C64D-XHM-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 550 ns
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT24C64D-XHM-T FAQ
1.How can I place an order for AT24C64D-XHM-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C64D-XHM-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C64D-XHM-T reliable?
The price and inventory of AT24C64D-XHM-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C64D-XHM-T is usually 5 days.
3.What payment methods are accepted for AT24C64D-XHM-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C64D-XHM-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C64D-XHM-T?
AT24C64D-XHM-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C64D-XHM-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C64D-XHM-T?
For technical support, including AT24C64D-XHM-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C64D-XHM-T requirements.
6.How does Aetrix verify that AT24C64D-XHM-T is sourced from the original manufacturer or authorized distributors?
All AT24C64D-XHM-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C64D-XHM-T meets industry standards.
7.What is the process for return or replacement of AT24C64D-XHM-T?
All AT24C64D-XHM-T units undergo pre-shipment inspection (PSI). If there is an issue with AT24C64D-XHM-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C64D-XHM-T part is unused and in its original packaging.
Return procedure for AT24C64D-XHM-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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