Microchip Technology AT24C64W-10SI-1.8
- Part No.:
- AT24C64W-10SI-1.8
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
AT24C64W-10SI-1.8.pdf
- Description:
- IC EEPROM 64KBIT I2C 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,684
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT24C64W-10SI-1.8 from Microchip Technology (formerly Atmel) is a 64 Kbit I²C-compatible serial EEPROM organized as 8192 × 8 bits, operating from 1.8 V to 5.5 V, featuring 32-byte page write capability, hardware write protection via WP pin, and 100 kHz clock rate at 1.8 V for low-power embedded systems.
For engineers reviewing the AT24C64W-10SI-1.8 datasheet, AT24C64W-10SI-1.8 pinout, AT24C64W-10SI-1.8 application, or AT24C64W-10SI-1.8 equivalent, key selection criteria include 1.8 V minimum supply, industrial temperature range (−40°C to +85°C), TSSOP-8 package, Schmitt-trigger inputs for noise immunity, and 1 million write cycles endurance.
Technical Context
The AT24C64W-10SI-1.8 implements a standard two-wire (I²C) interface with open-drain SDA and input-clocked SCL, supporting bidirectional data transfer and device addressing via A0–A2 pins. It uses internal address counters for sequential reads and supports both byte and 32-byte page writes with self-timed internal write cycles up to 10 ms.
Its architecture includes a dedicated Write Protect (WP) pin that disables writes to the upper quadrant (16 Kb) when pulled high, and Schmitt-triggered, filtered inputs on SDA/SCL to suppress noise in electrically noisy environments. Standby current is specified at 0.1 µA (typ.) at 1.8 V, enabling use in battery-backed and ultra-low-power applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8192 × 8), sufficient for firmware parameter storage, calibration data, or configuration registers in microcontroller-based systems. |
| Supply Voltage Range | 1.8 V to 5.5 V - enables direct interfacing with 1.8 V logic families and compatibility with mixed-voltage systems without level shifters. |
| Interface | 2-wire I²C (open-drain SDA, clocked SCL) - reduces PCB routing complexity and supports multi-drop bus with up to 8 devices using A0–A2 address pins. |
| Write Cycle Time | Max 10 ms - defines minimum interval between write commands; requires acknowledge polling or timeout handling in host firmware. |
| Endurance | 1 million write cycles - ensures long-term reliability in applications requiring frequent updates, such as metering or event logging. |
| Data Retention | 100 years at +25°C - guarantees nonvolatile data integrity over product lifetime without refresh or backup power. |
| Operating Temperature | −40°C to +85°C - qualified for industrial environments including automotive body control modules and factory automation controllers. |
| Package | TSSOP-8 (8A2), 4.4 mm body width - surface-mount, space-efficient footprint compatible with automated assembly and high-density PCB layouts. |
Pinout & Package
AT24C64W-10SI-1.8 is housed in an 8-pin Thin Shrink Small Outline Package (TSSOP-8, JEDEC MO-153 AA), measuring 3.0 mm × 4.4 mm × 1.05 mm, with gull-wing leads and pin 1 indicator in the top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Device Address Input | Hardwired low/high or left floating (internally pulled down) to configure one of eight possible I²C slave addresses on shared bus. |
| A1 | Device Address Input | Used with A0 and A2 to form 3-bit hardware address; enables cascading up to eight AT24C64W-10SI-1.8 devices on same I²C bus. |
| A2 | Device Address Input | Third address bit; all three (A2–A0) must match hardware wiring for device to respond to its assigned I²C address. |
| GND | Ground Reference | Return path for VCC and signal currents; must be low-impedance connection to minimize noise coupling into SDA/SCL lines. |
| VCC | Power Supply | 1.8 V to 5.5 V input; bypass capacitor (0.1 µF ceramic) required near pin to stabilize voltage during write cycles and reduce EMI. |
| WP | Write Protect Control | Active-high pin: tied to VCC to lock upper 16 Kb (2048 bytes); tied to GND or left unconnected for full memory writability. |
| SCL | Serial Clock Input | Positive-edge sampled clock for data-in; negative-edge sampled for data-out; requires external pull-up resistor (typically 2.2–10 kΩ). |
| SDA | Serial Data I/O | Bidirectional, open-drain line shared across I²C bus; requires same external pull-up as SCL; supports wire-OR with other open-drain devices. |
Key Features
| Feature | Design Value |
|---|---|
| Low-Voltage Operation | Functional down to 1.8 V supply - eliminates need for voltage regulators in 1.8 V SoC or FPGA subsystems, reducing BOM count and power loss. |
| Schmitt-Trigger Inputs | On SDA and SCL pins - rejects sub-microsecond noise transients common in motor drives or switching power supplies, improving bus robustness. |
| Page Write Mode | 32-byte burst writes - cuts firmware overhead by >90% vs. byte-wise writes for block updates (e.g., sensor calibration tables), accelerating field updates. |
| Hardware Write Protection | WP pin controls upper quadrant (16 Kb) lock - prevents accidental overwrite of critical boot parameters or security keys without software intervention. |
| High Endurance & Retention | 1M write cycles / 100-year data retention - validated for mission-critical logging in infrastructure equipment where replacement is impractical. |
| Industrial Temp Range | −40°C to +85°C operation - meets extended environmental requirements for outdoor gateways, industrial PLCs, and energy metering hardware. |
Applications
| Smart Energy Metering | Industrial PLC Configuration |
|---|---|
|
Use Scenario: Storing tariff schedules, meter calibration coefficients, and tamper-event logs in DIN-rail mounted electricity meters. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed via I²C by metering SoC; retains data across mains outages and firmware upgrades. Use Value: AT24C64W-10SI-1.8's 1.8 V operation allows direct interface with low-power metrology ADCs, while 1M endurance supports daily log writes for 27+ years. |
Use Scenario: Holding I/O mapping tables, PID tuning parameters, and safety-critical configuration flags in programmable logic controllers. IC Role / Device Role / Timing Role: Persistent configuration register bank; updated only during commissioning or maintenance, read at boot time. Use Value: Hardware WP pin prevents runtime corruption of safety-related settings; −40°C to +85°C rating ensures reliability inside sealed control cabinets. |
| Medical Diagnostic Device Calibration | Automotive Body Control Module |
|
Use Scenario: Storing sensor offset/gain values and diagnostic fault history in portable ultrasound or blood glucose analyzers. IC Role / Device Role / Timing Role: Calibration data vault; written once during factory calibration, read repeatedly during measurement cycles. Use Value: AT24C64W-10SI-1.8's 100-year data retention guarantees accuracy traceability over device lifetime, meeting ISO 13485 documentation requirements. |
Use Scenario: Saving seat/mirror position presets, door lock configurations, and lighting profiles in vehicle body control units. IC Role / Device Role / Timing Role: User preference storage accessed by MCU over I²C; survives battery disconnect and ECU reflash events. Use Value: TSSOP-8 package fits tight under-hood spaces; 1.8 V compatibility aligns with modern automotive MCUs' low-voltage IO domains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95640-DWDW3TP/K | 64 Kbit SPI interface, 2.5–5.5 V supply, 20 MHz max clock; no WP pin - uses software write enable. | Requires SPI-capable MCU; lacks hardware quadrant-level write protection; higher speed but less noise-immune than I²C. | Choose when system already uses SPI peripherals and needs faster random access; avoid if noise immunity or hardware lock is required. |
| BR24G64FJ-WE2 | 64 Kbit I²C, 1.6–5.5 V, 1 MHz clock at 5 V; built-in write protect register (not pin-based); 400 kHz at 1.8 V. | Software-configurable protection zones; higher 1.8 V clock rate enables faster bulk writes; different pinout (SOIC-8 only). | Prefer for designs needing finer-grained write control or higher throughput at 1.8 V; verify SOIC-8 footprint compatibility. |
Compared with M95640-DWDW3TP/K and BR24G64FJ-WE2, the AT24C64W-10SI-1.8 offers deterministic hardware write protection, proven Schmitt-trigger noise immunity, and TSSOP-8 packaging optimized for space-constrained industrial PCBs - making it optimal for safety-aware, low-noise, and size-sensitive applications.
Availability
AT24C64W-10SI-1.8 is available at Aetrix Electronics and suitable for smart metering, industrial PLC configuration, medical calibration storage, and automotive body control applications requiring stable component supply, long-lifecycle support, and guaranteed industrial-grade performance.
Supply support for AT24C64W-10SI-1.8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions, with a focus on reliability, longevity, and embedded system integration.
The AT24C64W-10SI-1.8 belongs to Microchip's legacy AT24Cxx serial EEPROM family, designed specifically for low-power, industrial-grade data logging and configuration storage in resource-constrained embedded systems.
FAQ
What is the maximum clock frequency supported by AT24C64W-10SI-1.8 at 1.8 V?
The AT24C64W-10SI-1.8 supports a maximum I²C clock frequency of 100 kHz when operating at 1.8 V, as specified in the AC Characteristics table. This is lower than its 400 kHz capability at 5 V but ensures reliable timing margins and noise immunity in low-voltage systems. The device automatically adapts to the applied VCC without configuration.
Does AT24C64W-10SI-1.8 require external pull-up resistors on SDA and SCL lines?
Yes, AT24C64W-10SI-1.8 requires external pull-up resistors on both SDA and SCL lines because its I²C interface uses open-drain outputs. Typical values range from 2.2 kΩ to 10 kΩ depending on bus capacitance and speed; 4.7 kΩ is commonly used for 100 kHz operation at 1.8 V to balance rise time and power consumption.
How does the Write Protect (WP) pin function on AT24C64W-10SI-1.8?
On AT24C64W-10SI-1.8, the WP pin is active-high: when tied to VCC, it inhibits writes to the upper quadrant (16 Kb, addresses 0x2000–0x3FFF); when tied to GND or left unconnected (internally pulled down), full memory is writable. This provides hardware-level protection against accidental firmware or configuration corruption.
Can AT24C64W-10SI-1.8 be used in place of AT24C64N-10SI-1.8?
AT24C64W-10SI-1.8 and AT24C64N-10SI-1.8 share identical electrical specifications and memory organization but differ in package: W = TSSOP-8 (8A2), N = JEDEC SOIC-8 (8S1). They are functionally interchangeable if the PCB layout accommodates the respective footprint and thermal/mechanical constraints of each package.
What is the standby current consumption of AT24C64W-10SI-1.8 at 1.8 V?
The standby current (ISB1) of AT24C64W-10SI-1.8 is characterized at 0.1 µA (typical) when VCC = 1.8 V and inputs are at VCC or VSS. This ultra-low quiescent draw makes it suitable for battery-powered devices where months or years of shelf life are required between wake-ups.
AT24C64W-10SI-1.8 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT24C64W-10SI-1.8 FAQ
1.How can I place an order for AT24C64W-10SI-1.8 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C64W-10SI-1.8 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C64W-10SI-1.8 reliable?
The price and inventory of AT24C64W-10SI-1.8 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C64W-10SI-1.8 is usually 5 days.
3.What payment methods are accepted for AT24C64W-10SI-1.8?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C64W-10SI-1.8 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C64W-10SI-1.8?
AT24C64W-10SI-1.8 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C64W-10SI-1.8 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C64W-10SI-1.8?
For technical support, including AT24C64W-10SI-1.8 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C64W-10SI-1.8 requirements.
6.How does Aetrix verify that AT24C64W-10SI-1.8 is sourced from the original manufacturer or authorized distributors?
All AT24C64W-10SI-1.8 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C64W-10SI-1.8 meets industry standards.
7.What is the process for return or replacement of AT24C64W-10SI-1.8?
All AT24C64W-10SI-1.8 units undergo pre-shipment inspection (PSI). If there is an issue with AT24C64W-10SI-1.8, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C64W-10SI-1.8 part is unused and in its original packaging.
Return procedure for AT24C64W-10SI-1.8:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT24C64W-10SI-1.8 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

