Microchip Technology AT24CS64-XHM-B
- Part No.:
- AT24CS64-XHM-B
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT24CS64-XHM-B.pdf
- Description:
- IC EEPROM 64KBIT I2C 1MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:617
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT24CS64-XHM-B from Microchip Technology is a 64-Kbit I²C-compatible serial EEPROM with factory-programmed 128-bit unique serial number, operating from 1.7V to 5.5V, supporting 1 MHz Fast Mode Plus, and featuring hardware write protection (WP), 32-byte page write, and industrial temperature range (–40°C to +85°C). It serves as nonvolatile configuration storage in embedded controllers, sensor nodes, and secure device authentication systems.
For engineers reviewing the AT24CS64-XHM-B datasheet, AT24CS64-XHM-B pinout, AT24CS64-XHM-B application, or AT24CS64-XHM-B equivalent, key selection criteria include its guaranteed-unique 128-bit serial number (non-volatile, read-only, separate from user memory), ultra-low standby current (≤6 µA at 5.0V), 1,000,000 write endurance, 100-year data retention, and support for cascaded multi-device I²C bus configurations up to eight units.
Technical Context
The AT24CS64-XHM-B implements a two-wire I²C slave interface with Schmitt-triggered, noise-filtered SDA/SCL inputs, enabling robust operation in electrically noisy environments. Its internal architecture includes dedicated hardware address comparators (A0–A2), a high-voltage generation circuit for EEPROM programming, and independent 128-bit serial number memory block mapped to device address '1011b' - physically isolated from the 8,192 × 8 user array.
It supports three I²C speed modes: 100 kHz (1.7–5.5V), 400 kHz (1.7–5.5V), and 1 MHz Fast Mode Plus (2.5–5.5V), with self-timed write cycles completing in ≤5 ms. The WP pin provides full-array hardware write protection, and all address/control pins (A0–A2, WP) feature strong internal pull-downs that disengage only when biased above ~0.5×VCC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized in 256 pages of 32 bytes each |
| Interface | I²C-compatible two-wire bus with 100/400 kHz Standard/Fast mode and 1 MHz Fast Mode Plus support |
| VCC Range | 1.7V to 5.5V - enables direct interfacing with 1.8V, 2.5V, 3.3V, and 5V microcontrollers |
| Serial Number | 128-bit factory-programmed, permanently locked, globally unique across entire CS Series, zero user memory overhead |
| Write Endurance | 1,000,000 cycles - validated at 25°C, 3.3V, page-write mode |
| Data Retention | 100 years at 55°C - ensures long-term reliability in industrial deployments |
| Standby Current | ≤6 µA at VCC = 5.0V - critical for battery-powered endpoint devices |
| Operating Temp | –40°C to +85°C - qualified for industrial-grade environmental stress |
Pinout & Package
AT24CS64-XHM-B is supplied in an 8-pad UDFN package (2 mm × 3 mm, 0.5 mm pitch) with exposed pad (recommended to connect to GND). Pin functions are identical across SOIC, TSSOP, and UDFN variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Hardware Device Address Input | Configures LSB of 7-bit I²C slave address; internally pulled down if floating - must be tied to known logic level for deterministic multi-device bus addressing |
| A1 | Hardware Device Address Input | Configures middle bit of 7-bit I²C slave address; same internal pull-down behavior as A0 - required for reliable bus arbitration in multi-drop systems |
| A2 | Hardware Device Address Input | Configures MSB of 7-bit I²C slave address; enables up to eight AT24CS64-XHM-B devices on one bus without software address conflict |
| GND | Power Ground Reference | System return path for VCC and all I/O; exposed pad in UDFN should be connected to GND for thermal and EMI performance |
| SDA | Open-Drain Bidirectional Data Line | Carries I²C data and ACK/NACK; requires external pull-up resistor ≤10 kΩ; wire-OR compatible with other open-drain devices |
| SCL | Input Clock Line | Controls data sampling timing; rising edge latches input, falling edge outputs data; must be pulled high externally or driven actively |
| WP | Hardware Write-Protect Input | At VCC: disables all writes to entire memory array; at GND: enables normal write operations; internally pulled down if floating |
| VCC | Power Supply Input | Supplies core logic and EEPROM programming voltage; slew rate limited to ≤0.1 V/µs during power-up to ensure POR stability |
Key Features
| Feature | Design Value |
|---|---|
| Factory-Programmed Serial Number | 128-bit value permanently written during wafer sort - eliminates production-line serialization overhead and guarantees uniqueness across all Microchip CS-series EEPROMs |
| Multi-Voltage I²C Interface | Supports 100/400 kHz at 1.7–5.5V and 1 MHz FM+ at 2.5–5.5V - enables seamless integration into mixed-voltage systems without level shifters |
| Hardware Write Protection | WP pin disables all write operations when driven high - provides fail-safe data integrity independent of firmware state or communication errors |
| Noise-Resilient Inputs | Schmitt triggers + digital filtering on SDA/SCL - suppresses >100 ns glitches and improves immunity to EMI in motor drives or industrial PLCs |
| Low-Power Operation | 3 mA max active current and 6 µA max standby current at 5.0V - extends battery life in portable medical sensors and IoT edge nodes |
| High-Reliability Memory | 1,000,000 write cycles and 100-year data retention at 55°C - meets long-lifecycle requirements for infrastructure monitoring and automotive subsystems |
Applications
| Secure Device Authentication | Industrial Sensor Calibration Storage |
|---|---|
Use Scenario: Embedded system verifies authenticity of field-replaceable modules (e.g., camera lenses, medical probes) using cryptographic challenge-response with device-unique serial number. IC Role / Device Role / Timing Role: Nonvolatile identity anchor providing immutable 128-bit identifier; accessed via I²C during boot or hot-swap detection. Use Value: Eliminates need for external secure elements or firmware-based key management - reduces BOM cost and attack surface while ensuring traceability. | Use Scenario: Factory calibration coefficients for pressure, temperature, or humidity sensors are stored post-test and recalled at power-on. IC Role / Device Role / Timing Role: Persistent configuration memory holding offset/gain values; read during initialization before sensor data acquisition begins. Use Value: Enables single-pass calibration without reprogramming microcontroller flash; supports field recalibration via service tools using standard I²C commands. |
| Smart Energy Meter Configuration | Automotive Body Control Module (BCM) |
Use Scenario: Utility meter stores tariff schedules, billing history, and tamper logs across power cycles and firmware updates. IC Role / Device Role / Timing Role: Robust nonvolatile logging buffer; writes occur asynchronously during meter events, reads during HMI display refresh or remote reporting. Use Value: Guarantees data persistence under brownout conditions due to 1.7V operation and fast 5 ms write cycle - prevents revenue loss from lost consumption records. | Use Scenario: BCM retains seat/mirror position memory, lighting profiles, and diagnostic trouble codes (DTCs) across ignition cycles. IC Role / Device Role / Timing Role: Low-power configuration store accessed over vehicle I²C bus; WP pin tied to ignition signal for write-lock during engine run. Use Value: Meets automotive AEC-Q100 Class 2 temp range (–40°C to +105°C derated) and supports 100k+ lifetime write cycles required for user preference storage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C64D-SSHM-T | No factory-programmed serial number; identical 64-Kbit density, I²C interface, and 1.7–5.5V operation; same UDFN-8 package | Lacks hardware-unique identity - unsuitable for secure authentication or anti-cloning use cases | Select when only basic nonvolatile storage is needed and serialization is handled in MCU firmware or external security IC |
| M95640-DRMN6TP/K | 64-Kbit SPI interface (not I²C); operates 1.8–5.5V; 5 ms write cycle; no serial number; SO8 package | Requires SPI host controller instead of I²C; incompatible pinout and protocol - necessitates PCB and firmware redesign | Choose only if existing design uses SPI peripherals and board layout cannot accommodate I²C routing or UDFN footprint |
Compared with AT24C64D-SSHM-T, the AT24CS64-XHM-B adds irreplaceable secure identity capability without sacrificing power or endurance; versus M95640-DRMN6TP/K, it preserves I²C compatibility and UDFN space savings but requires no interface migration effort.
Availability
AT24CS64-XHM-B is available at Aetrix Electronics and suitable for industrial sensor nodes, secure peripheral authentication, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant green packaging.
Supply support for AT24CS64-XHM-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global manufacturing and support infrastructure.
The AT24CS64-XHM-B belongs to Microchip's CS-series serial EEPROM product line, engineered specifically for applications demanding guaranteed-unique device identity, low-voltage I²C interoperability, and extended data retention in harsh environments.
FAQ
What is the function of the WP pin on the AT24CS64-XHM-B?
The WP (Write-Protect) pin on the AT24CS64-XHM-B provides hardware-level inhibition of all write operations to the memory array. When WP is driven to VCC, the entire 64-Kbit EEPROM is locked against modification; when grounded, normal byte and page writes are enabled. If left floating, the pin is internally pulled down to GND - but Microchip recommends tying it to a defined logic level to prevent noise-induced misoperation. This feature ensures data integrity even during firmware crashes or power transients.
Does the AT24CS64-XHM-B require external pull-up resistors on SDA and SCL lines?
Yes, the AT24CS64-XHM-B requires external pull-up resistors on both SDA and SCL lines because its SDA pin is open-drain and SCL is a CMOS input. Microchip specifies maximum pull-up values of 10 kΩ for 100 kHz, 4 kΩ for 400 kHz, and 1.3 kΩ for 1 MHz operation - selected based on bus capacitance and speed requirements. Failure to install appropriate pull-ups will result in communication failure or intermittent I²C bus lockup.
How is the 128-bit serial number accessed on the AT24CS64-XHM-B?
The 128-bit serial number on the AT24CS64-XHM-B is accessed via the I²C bus using a dedicated device address prefix of '1011b' (0xB0–0xBF), distinct from the main memory's '1010b' (0xA0–0xAF) base address. It resides in a separate, read-only memory block that consumes no user memory space and cannot be overwritten. Reading requires sending a START condition, the 0xBx address byte, then reading 16 consecutive bytes - the same protocol used for standard EEPROM reads but targeting the alternate address space.
What is the maximum write cycle time for the AT24CS64-XHM-B?
The maximum write cycle time for the AT24CS64-XHM-B is 5 ms, applicable to both byte and page write operations. This self-timed internal programming duration is guaranteed across the full operating voltage (1.7–5.5V) and temperature (–40°C to +85°C) ranges. During this period, the device does not acknowledge I²C commands - host systems must implement acknowledge polling or fixed-delay waits before issuing subsequent operations to avoid bus errors.
Is the AT24CS64-XHM-B compatible with standard I²C bus speeds and protocols?
Yes, the AT24CS64-XHM-B is fully compatible with standard I²C protocols: it supports Standard Mode (100 kHz), Fast Mode (400 kHz), and Fast Mode Plus (1 MHz) across its specified VCC range. It implements standard START/STOP conditions, 9-bit ACK/NACK handshaking, and MSB-first data transmission. Its Schmitt-triggered, filtered inputs meet I²C noise immunity requirements, and its open-drain SDA output conforms to I²C electrical specifications - enabling drop-in replacement in existing I²C designs without protocol changes.
AT24CS64-XHM-B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 550 ns
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT24CS64-XHM-B FAQ
1.How can I place an order for AT24CS64-XHM-B through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24CS64-XHM-B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24CS64-XHM-B reliable?
The price and inventory of AT24CS64-XHM-B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24CS64-XHM-B is usually 5 days.
3.What payment methods are accepted for AT24CS64-XHM-B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24CS64-XHM-B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24CS64-XHM-B?
AT24CS64-XHM-B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24CS64-XHM-B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24CS64-XHM-B?
For technical support, including AT24CS64-XHM-B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24CS64-XHM-B requirements.
6.How does Aetrix verify that AT24CS64-XHM-B is sourced from the original manufacturer or authorized distributors?
All AT24CS64-XHM-B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24CS64-XHM-B meets industry standards.
7.What is the process for return or replacement of AT24CS64-XHM-B?
All AT24CS64-XHM-B units undergo pre-shipment inspection (PSI). If there is an issue with AT24CS64-XHM-B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24CS64-XHM-B part is unused and in its original packaging.
Return procedure for AT24CS64-XHM-B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT24CS64-XHM-B Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
