Microchip Technology AT25010-10PI
- Part No.:
- AT25010-10PI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT25010-10PI.pdf
- Description:
- IC EEPROM 1KBIT SPI 3MHZ 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,329
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Product details
Overview
AT25010-10PI from Atmel (now Microchip) is a 1-Kbit SPI serial EEPROM organized as 128 × 8 bits, operating across 2.7V–5.5V supply range with industrial temperature rating (−40°C to +85°C), 2.1 MHz max clock rate at 5V, and 8-byte page write capability. It serves as nonvolatile configuration storage in microcontroller-based systems requiring low-power, pin-efficient memory with hardware/software write protection.
For engineers reviewing the AT25010-10PI datasheet, AT25010-10PI pinout, AT25010-10PI application, or AT25010-10PI equivalent, key selection considerations include its PDIP/SOIC package compatibility, SPI Mode 0/3 support, block-level write protection (1/4, 1/2, or full array), self-timed 10 ms write cycle, and 1 million endurance cycles - all validated for industrial-grade embedded control and sensor calibration use cases.
Technical Context
The AT25010-10PI implements a synchronous SPI slave interface with dedicated SI (input), SO (output), SCK (clock), and CS (chip select) pins, supporting MSB-first 8-bit op-code + address + data framing. Its internal architecture includes an 8-bit instruction register, nonvolatile status register (BP1/BP0/WEN/RDY), and automatic address incrementing during sequential reads or page writes.
Write operations require explicit WREN instruction followed by WRITE command; hardware protection is enforced via WP pin assertion, while HOLD pin enables communication suspension without sequence reset. All programming is self-timed with no external erase step, and the device powers up in write-disabled state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1024 bits (128 words × 8 bits), sufficient for firmware flags, calibration coefficients, or small configuration tables |
| Interface | SPI slave (Modes 0 and 3), eliminating need for parallel bus routing or address latches |
| Supply Voltage Range | 2.7V to 5.5V - supports mixed-voltage systems including 3.3V microcontrollers and legacy 5V logic |
| Max Clock Frequency | 2.1 MHz at 5V - enables fast parameter updates without CPU overhead in real-time control loops |
| Write Cycle Time | 10 ms maximum - deterministic latency for critical nonvolatile writes, e.g., fault log recording |
| Endurance & Retention | 1 million write cycles / 100-year data retention - suitable for field-deployed equipment with infrequent but mission-critical updates |
| Temperature Range | −40°C to +85°C industrial grade - qualified for automotive body control modules and industrial PLC I/O expansion |
Pinout & Package
AT25010-10PI is supplied in 8-pin PDIP (package code 8P3) with 0.300" width, compatible with through-hole prototyping and legacy PCB layouts. Pin functions are electrically identical to the JEDEC SOIC variant (8S1), enabling drop-in replacement where board space permits.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable: asserts SPI transaction start; high-Z SO when deasserted prevents bus contention |
| SCK | Serial Clock | Master-generated edge-triggered clock; timing defines setup/hold windows for SI/SO sampling |
| SI | Serial Data Input | Receives op-codes, addresses, and write data; ignored during HOLD or when CS is high |
| SO | Serial Data Output | Drives read data and status bits; enters high-impedance state when CS is high or HOLD is active |
| WP | Write Protect | Hardware lock: low disables all write instructions regardless of WREN status or status register settings |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer without resetting internal address counter or command state |
| VCC | Power Supply | 2.7–5.5V operation enables direct connection to MCU VDD rails without LDO buffering |
| GND | Ground Reference | Common return path for logic and power; decoupling capacitor required within 10 mm of VCC/GND pins |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Configurable via status register to lock 1/4, 1/2, or entire memory array - prevents accidental overwrites of boot parameters or security keys |
| Page Write Mode | 8-byte burst writes reduce transaction count by 8× vs. byte-wise programming - cuts SPI bus occupancy and host CPU load |
| Dual Write Protection | Combines hardware (WP pin) and software (WREN + status register) layers - meets IEC 61508 functional safety requirements for write-critical systems |
| Industrial Temperature Rating | Validated operation from −40°C to +85°C - eliminates derating concerns in uncontrolled environments like factory floors or outdoor enclosures |
| ESD Robustness | ≥4000V HBM - withstands handling and system-level ESD events without latch-up or data corruption |
Applications
| Industrial Sensor Calibration | Automotive Body Control Module |
|---|---|
Use Scenario: Storing temperature-compensated offset/gain coefficients for analog sensor front-ends during factory calibration. IC Role / Device Role / Timing Role: Nonvolatile configuration store accessed once per power-on reset; requires guaranteed write integrity after calibration. Use Value: 1M endurance ensures >10 years of recalibration cycles; block protection prevents overwrite of calibrated values during firmware updates. |
Use Scenario: Retaining user preferences (window position, mirror angle, seat settings) across ignition cycles in entry-level vehicles. IC Role / Device Role / Timing Role: Low-power EEPROM interfaced to 8-bit MCU via SPI; must retain data during battery disconnect. Use Value: 2.7V min VCC supports operation down to weak battery conditions; 100-year retention guarantees data survival over vehicle lifetime. |
| Medical Device Configuration | Smart Energy Meter Firmware Flags |
Use Scenario: Holding regulatory-compliant operational limits (e.g., max infusion rate, alarm thresholds) that must survive power loss and resist tampering. IC Role / Device Role / Timing Role: Secure configuration vault with hardware write lock; accessed only during service mode. Use Value: WP pin hardwired low in production units enforces immutable settings; status register BP bits provide secondary lock for field upgrades. |
Use Scenario: Storing tariff schedules, meter ID, and cryptographic keys in utility-grade electricity meters deployed in harsh outdoor substations. IC Role / Device Role / Timing Role: Industrial-grade nonvolatile memory co-located with metrology SoC; operates continuously at elevated ambient temperatures. Use Value: −40°C to +85°C rating ensures reliability at transformer-level heat; 10 ms write time enables rapid key rotation during secure boot. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95128-WMN6TP | 128 Kbit capacity, 20 MHz SPI, 1.8V–5.5V, SO8 only - no PDIP option | Higher density for complex parameter sets; lacks industrial temp grade in base variant | Select when >1 Kbit storage is needed and SOIC-only assembly is acceptable |
| BR24G01FJ-3GE2 | I²C interface (not SPI), 1 Kbit, 1.7V–5.5V, −40°C to +105°C, 400 kHz max - slower, different protocol stack | Requires I²C-capable MCU; wider temp range but incompatible with SPI-only designs | Choose only if existing design uses I²C and needs extended high-temp margin |
Compared with M95128-WMN6TP and BR24G01FJ-3GE2, the AT25010-10PI offers verified SPI Mode 0/3 interoperability with legacy 8051/HC11 MCUs, PDIP package for manual repairability, and precise industrial-grade qualification - making it optimal for cost-sensitive, field-serviceable embedded systems where protocol and package continuity are mandatory.
Availability
AT25010-10PI is available at Aetrix Electronics and suitable for industrial sensor calibration, automotive body control modules, medical device configuration, and smart energy meter firmware flag storage requiring stable component supply across long-lifecycle programs.
Supply support for AT25010-10PI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation, now part of Microchip Technology, designs high-reliability nonvolatile memory and microcontroller solutions for industrial, automotive, and consumer applications.
The AT25010-10PI belongs to Atmel's SPI serial EEPROM product line, engineered specifically for low-pin-count, low-power embedded systems needing robust, field-programmable configuration storage with hardware-enforced data integrity.
FAQ
What is the maximum clock frequency supported by the AT25010-10PI at 3.3V operation?
The AT25010-10PI supports up to 2.1 MHz at 5.0V, but its AC characteristics specify 2.1 MHz only for VCC = 4.5–5.5V. At 3.3V (within 2.7–5.5V range), the maximum clock frequency is 2.1 MHz per the -2.7 voltage option characterization - confirmed in the AC Characteristics table under "2.7–5.5V" column for fSCK. This allows full-speed operation with common 3.3V microcontrollers without derating.
Does the AT25010-10PI require an external pull-up resistor on the SO pin?
No, the AT25010-10PI does not require an external pull-up on the SO pin. Its SO output is actively driven high or low during read operations and enters a defined high-impedance state when CS is high or HOLD is asserted. External pull-ups may cause bus contention or increased standby current and are explicitly omitted in all reference schematics for this device.
How does the HOLD pin function during an active write cycle?
The HOLD pin cannot suspend an internal write cycle once initiated - it only affects serial communication. If HOLD is asserted during a write, the SO pin goes high-impedance and SI input is ignored, but the self-timed 10 ms write continues uninterrupted. The RDY bit (status register Bit 0) remains '1' until completion, and RDSR remains accessible to monitor progress.
Can the AT25010-10PI be used with SPI Mode 1 or Mode 2 interfaces?
No, the AT25010-10PI explicitly supports only SPI Modes 0 (CPOL=0, CPHA=0) and 3 (CPOL=1, CPHA=1), as stated in its Features section. Attempting Mode 1 or Mode 2 will result in misaligned sampling of SI/SO relative to SCK edges, causing command rejection or corrupted data transfers. MCU SPI peripherals must be configured accordingly.
What happens if the WP pin is pulled low during a WREN instruction?
If WP is low during WREN execution, the AT25010-10PI ignores the instruction and remains in write-disabled state. The WREN command requires WP = high to set the Write Enable Latch (WEN bit); pulling WP low invalidates the enable attempt, and subsequent WRITE commands will be rejected even if CS and timing are correct.
AT25010-10PI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 3 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT25010-10PI FAQ
1.How can I place an order for AT25010-10PI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25010-10PI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25010-10PI reliable?
The price and inventory of AT25010-10PI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25010-10PI is usually 5 days.
3.What payment methods are accepted for AT25010-10PI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25010-10PI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25010-10PI?
AT25010-10PI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25010-10PI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25010-10PI?
For technical support, including AT25010-10PI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25010-10PI requirements.
6.How does Aetrix verify that AT25010-10PI is sourced from the original manufacturer or authorized distributors?
All AT25010-10PI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25010-10PI meets industry standards.
7.What is the process for return or replacement of AT25010-10PI?
All AT25010-10PI units undergo pre-shipment inspection (PSI). If there is an issue with AT25010-10PI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25010-10PI part is unused and in its original packaging.
Return procedure for AT25010-10PI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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