Microchip Technology AT25010AN-10SI-2.7
- Part No.:
- AT25010AN-10SI-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25010AN-10SI-2.7.pdf
- Description:
- IC EEPROM 1KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,541
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25010AN-10SI-2.7 from Microchip Technology (formerly Atmel) is a 1-Kbit SPI serial EEPROM organized as 128 words × 8 bits, operating from 2.7V to 5.5V with 20 MHz max clock rate at 5V, 8-byte page write capability, and hardware/software write protection-used for configuration storage in industrial microcontroller systems.
For engineers reviewing the AT25010AN-10SI-2.7 datasheet, AT25010AN-10SI-2.7 pinout, AT25010AN-10SI-2.7 application, or AT25010AN-10SI-2.7 equivalent, key selection factors include VCC range compatibility (2.7–5.5V), SOIC-8 package footprint, SPI Mode 0/3 support, 1M endurance cycles, and block-level write protection via status register BP0/BP1 bits.
Technical Context
The AT25010AN-10SI-2.7 implements a synchronous slave SPI interface with dedicated SI/SO pins, CS-controlled selection, and HOLD/ WP pins for suspend and hardware write inhibit. It uses an 8-bit instruction register with MSB-first transmission and supports read/write operations without pre-erase.
Internal architecture includes a 128×8 memory array, status register with RDY/WEN/BP bits, and self-timed write cycle (≤5 ms). Block protection is nonvolatile and configurable to 0%, 25%, 50%, or 100% of array via WRSR instruction; WP pin override takes precedence over software protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1024 bits (128 × 8), sufficient for small firmware config or calibration data storage |
| Interface | SPI slave with CS/SCK/SI/SO/HOLD/WP - compatible with 68HC11, PIC, ARM Cortex-M MCU peripherals |
| Supply Voltage | 2.7V to 5.5V - supports mixed-voltage industrial designs without level-shifting |
| Max Clock Rate | 20 MHz at 5V - enables fast parameter loading during boot or runtime updates |
| Write Endurance | 1 million cycles - suitable for logging or dynamic parameter storage with frequent updates |
| Data Retention | 100 years - ensures long-term reliability in unpowered storage applications |
| Operating Temp | −40°C to +85°C - qualified for industrial ambient environments |
Pinout & Package
AT25010AN-10SI-2.7 is packaged in an 8-lead JEDEC SOIC (8S1), 0.150" wide, surface-mount package with standard gull-wing leads and 1.27 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable; must be low to accept instructions; high-Z SO when CS high |
| SCK | Serial Clock | Master-generated edge-triggered clock; timing defines setup/hold windows per Table 4 |
| SI | Serial Data Input | MSB-first instruction/address/data input; ignored during HOLD or write cycle |
| SO | Serial Data Output | MSB-first data output; high-impedance when CS high or during internal write |
| GND | Ground Reference | Return path for VCC and all I/O; requires low-impedance PCB plane for noise immunity |
| VCC | Power Supply | 2.7–5.5V supply; decoupling capacitor (0.1 µF) required near pin per layout guidelines |
| WP | Write Protect | Hardware lock: low = all writes inhibited regardless of WREN or status register state |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer without resetting sequence; requires SCK low to assert |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Mode | 8-byte burst programming reduces total write time vs. byte-by-byte; address auto-increments within page |
| Block Write Protection | Four nonvolatile protection levels (none / 1/4 / 1/2 / full array) controlled by BP0/BP1 bits in status register |
| Dual Write Protection | Combines hardware (WP pin) and software (WREN + status register) layers to prevent accidental writes |
| Self-timed Write Cycle | No external timing control needed; internal logic completes erase+write in ≤5 ms; RDSR bit 0 indicates busy state |
| Industrial Temperature Range | −40°C to +85°C operation with guaranteed AC/DC specs - validated for extended thermal cycling |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping, scaling coefficients, and user-defined alarm thresholds in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via SPI during power-up or field reconfiguration. Use Value: Enables field-upgradable settings without firmware change; 1M endurance supports >10 years of daily recalibration cycles. |
Use Scenario: Holding sensor offset/gain trim values and regulatory compliance logs in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure, low-power EEPROM interfaced to ARM Cortex-M0+ MCU for post-manufacturing calibration. Use Value: 2.7–5.5V operation matches battery-backed MCU rails; WP pin prevents corruption during brown-out events. |
| Automotive Body Control Module | Smart Energy Meter Firmware Settings |
Use Scenario: Retaining seat/mirror position presets, lighting profiles, and door lock behavior across ignition cycles. IC Role / Device Role / Timing Role: SPI EEPROM co-located with 8-bit automotive MCU; accessed during wake-up initialization. Use Value: −40°C to +85°C rating meets AEC-Q100 Grade 3 requirements; HOLD pin allows safe MCU interrupt handling during reads. |
Use Scenario: Storing tariff schedules, meter ID, and tamper-event timestamps in utility-grade electricity meters. IC Role / Device Role / Timing Role: Trusted configuration store with dual protection (WP + WRSR) against unauthorized firmware modification. Use Value: 100-year data retention ensures lifetime validity of billing parameters; SOIC-8 footprint simplifies automated assembly. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95128-WMN6TP | 128 Kbit capacity, same SOIC-8, 2.5–5.5V, 20 MHz, but lacks HOLD pin and has different status register layout | Higher density for multi-parameter tables; no suspend capability limits use in real-time interrupt contexts | Select when >1K storage needed and HOLD is unused; verify SPI timing margins per Table 4 |
| CAT25010VI-GT3 | 1 Kbit, SOIC-8, 1.8–5.5V, 10 MHz max, identical pinout and instruction set, but lower max clock and wider VCC range | Supports 1.8V systems (e.g., ultra-low-power MCUs); trade-off is 50% slower write throughput at 5V | Choose for 1.8V designs or where 10 MHz suffices; drop-in replacement if timing budget permits |
Compared with AT25010AN-10SI-2.7, M95128-WMN6TP offers higher density but removes HOLD functionality critical for deterministic MCU interrupt response, while CAT25010VI-GT3 provides broader voltage flexibility at reduced speed-making AT25010AN-10SI-2.7 optimal for 2.7–5.5V industrial systems requiring 20 MHz throughput and communication suspension.
Availability
AT25010AN-10SI-2.7 is available at Aetrix Electronics and suitable for industrial PLCs, medical calibration systems, automotive body controllers, and smart energy meters requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for AT25010AN-10SI-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel memory products, including qualification, documentation, and long-term supply assurance.
The AT25010A family was designed specifically for robust, low-power serial configuration storage in industrial and automotive microcontroller subsystems, emphasizing SPI interoperability, write protection integrity, and extended temperature reliability.
FAQ
What is the maximum clock frequency supported by AT25010AN-10SI-2.7?
The AT25010AN-10SI-2.7 supports up to 20 MHz SCK frequency when operated at 5.0V (VCC = 4.5–5.5V), 10 MHz at 2.7–5.5V, and 5 MHz at 1.8–3.6V per Table 4. The actual usable rate depends on VCC level and signal integrity; for 2.7V operation, 10 MHz is the verified maximum. AT25010AN-10SI-2.7 must be configured for SPI Mode 0 or Mode 3 to ensure correct sampling.
Does AT25010AN-10SI-2.7 require an external pull-up resistor on the SO pin?
No, AT25010AN-10SI-2.7 features an active push-pull SO driver and does not require an external pull-up. The SO pin transitions between valid VOH/VOL levels and high-impedance states based on CS and internal write status. External pull-ups may cause bus contention or violate VOL specifications, especially during HOLD or write cycles when SO is intentionally tri-stated.
How does the HOLD pin function during an active SPI transaction with AT25010AN-10SI-2.7?
The HOLD pin suspends serial communication without resetting the instruction sequence: it must be asserted low while SCK is low, freezing data flow on SI/SO and halting internal address counters. To resume, HOLD is returned high while SCK remains low. AT25010AN-10SI-2.7 retains all context-including partial op-code, address, and data-and continues from the exact bit position upon resumption.
Can AT25010AN-10SI-2.7 be used in 1.8V systems?
No - AT25010AN-10SI-2.7 is specified only for 2.7V to 5.5V operation (denoted by "-2.7" suffix). For 1.8V systems, the pin-compatible AT25010AN-10SI-1.8 variant must be used, which guarantees DC/AC performance down to 1.8V. Using AT25010AN-10SI-2.7 below 2.7V risks unreliable read/write behavior and violates absolute maximum ratings.
What happens if the WP pin is pulled low during a write cycle of AT25010AN-10SI-2.7?
If WP is driven low after CS falls but before the internal write cycle begins, AT25010AN-10SI-2.7 aborts the write and returns to standby. If WP goes low after the internal write has started (i.e., after CS rising edge), the ongoing write completes normally - WP only blocks new write initiation, not execution. This behavior ensures data integrity for in-progress updates while preventing new commands.
AT25010AN-10SI-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25010AN-10SI-2.7 FAQ
1.How can I place an order for AT25010AN-10SI-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25010AN-10SI-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25010AN-10SI-2.7 reliable?
The price and inventory of AT25010AN-10SI-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25010AN-10SI-2.7 is usually 5 days.
3.What payment methods are accepted for AT25010AN-10SI-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25010AN-10SI-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25010AN-10SI-2.7?
AT25010AN-10SI-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25010AN-10SI-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25010AN-10SI-2.7?
For technical support, including AT25010AN-10SI-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25010AN-10SI-2.7 requirements.
6.How does Aetrix verify that AT25010AN-10SI-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25010AN-10SI-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25010AN-10SI-2.7 meets industry standards.
7.What is the process for return or replacement of AT25010AN-10SI-2.7?
All AT25010AN-10SI-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25010AN-10SI-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25010AN-10SI-2.7 part is unused and in its original packaging.
Return procedure for AT25010AN-10SI-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25010AN-10SI-2.7 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
