Microchip Technology AT25010AN-10SU-1.8-T
- Part No.:
- AT25010AN-10SU-1.8-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25010AN-10SU-1.8-T.pdf
- Description:
- IC EEPROM 1KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT25010AN-10SU-1.8-T from Microchip Technology (formerly Atmel) is a 1-Kbit SPI serial EEPROM organized as 128 words × 8 bits, operating from 1.8 V to 5.5 V with 20 MHz max clock rate at 5 V, 8-byte page write capability, and industrial temperature range (−40°C to +85°C). It serves as nonvolatile configuration storage in microcontroller-based embedded systems requiring low-voltage operation and robust data retention.
For engineers reviewing the AT25010AN-10SU-1.8-T datasheet, AT25010AN-10SU-1.8-T pinout, AT25010AN-10SU-1.8-T application, or AT25010AN-10SU-1.8-T equivalent, key selection criteria include 1.8 V minimum supply voltage, SPI Mode 0/3 compatibility, hardware write protection via WP pin, HOLD pin for communication suspension, and TSSOP-8 packaging for space-constrained PCB layouts.
Technical Context
The AT25010AN-10SU-1.8-T implements a synchronous serial peripheral interface (SPI) slave architecture with separate SI (input) and SO (output) pins, supporting MSB-first transmission and op-code–driven instruction set including WREN, WRITE, READ, RDSR, and WRSR. Its internal status register controls block write protection (BP1/BP0) and ready/busy flag (RDY).
It features self-timed internal write cycles (≤5 ms), no erase-before-write requirement, and dual-layer data protection: software-enabled via WREN/WRSR and hardware-enforced via WP pin assertion. The HOLD pin allows pausing active SPI transactions without resetting the sequence, enabling multi-device arbitration on shared buses.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1024 bits (128 × 8), sufficient for firmware boot flags, calibration coefficients, or device ID storage in compact systems. |
| Supply Voltage Range | 1.8 V to 5.5 V - enables direct interfacing with 1.8 V, 2.7 V, 3.3 V, and 5 V logic domains without level shifters. |
| Max Clock Frequency | 20 MHz at VCC = 5 V - supports high-throughput configuration loading in time-critical applications. |
| Write Cycle Time | ≤5 ms - defines worst-case latency for persistent state updates; impacts system responsiveness during parameter saves. |
| Endurance | 1 million write cycles - ensures reliable field operation over 10+ years in logging or counter applications with daily writes. |
| Data Retention | 100 years at 25°C - guarantees long-term integrity of stored calibration or security keys without refresh. |
| Operating Temperature | −40°C to +85°C - validated for industrial control, automotive body electronics, and outdoor sensor nodes. |
Pinout & Package
AT25010AN-10SU-1.8-T uses an 8-lead Thin Shrink Small Outline Package (TSSOP), JEDEC-compliant 8A2 footprint (3.00 mm × 4.40 mm body, 0.65 mm pitch), RoHS-compliant and halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable; must be low to accept instructions; high impedance on SO when CS high. |
| SCK | Serial Clock Input | Master-generated clock; timing reference for SI/SO data sampling per SPI Mode 0 or 3. |
| SI | Serial Data Input | Receives op-codes, addresses, and write data; MSB first; ignored during HOLD or write cycle. |
| SO | Serial Data Output | Drives read data and status register bits; high-impedance when CS high or during HOLD. |
| GND | Ground Reference | Return path for all I/O and power currents; must be low-impedance to minimize noise coupling. |
| VCC | Power Supply | 1.8–5.5 V input; decoupling capacitor (0.1 µF) required near pin to suppress switching transients. |
| WP | Write Protect | Hardware lock: low disables all write operations regardless of WREN status or status register settings. |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer when pulled low while SCK is low; resumes on rising edge with SCK low. |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode 0 & 3 Support | Compatible with 6805/68HC11 and modern ARM Cortex-M SPI peripherals without mode reconfiguration. |
| 8-byte Page Write | Reduces total programming time vs. byte-wise writes; enables efficient bulk updates of adjacent memory locations. |
| Block Write Protection | Four selectable protection levels (none, 1/4, 1/2, full array) via nonvolatile BP1/BP0 bits in status register. |
| Hardware + Software Write Protection | WP pin provides fail-safe lock; WREN/WRSR allow dynamic, instruction-controlled access control. |
| HOLD Pin Functionality | Enables deterministic bus arbitration in multi-slave systems without interrupting or restarting serial sequences. |
Applications
| Industrial Sensor Calibration | Consumer IoT Device Configuration |
|---|---|
|
Use Scenario: Storing factory-calibrated ADC offset/gain coefficients and temperature compensation tables in smart pressure sensors. IC Role / Device Role / Timing Role: Nonvolatile configuration storage accessed during power-up initialization and runtime correction routines. Use Value: Ensures measurement accuracy across temperature and lifetime without external calibration hardware or host intervention. |
Use Scenario: Persisting Wi-Fi credentials, user preferences, and firmware update state in battery-powered smart thermostats. IC Role / Device Role / Timing Role: Low-power serial memory interfaced to MCU SPI port during boot and network provisioning phases. Use Value: Enables seamless reconnection after power loss and retains settings through 10+ years of operation. |
| Automotive Body Control Module | Medical Diagnostic Equipment |
|
Use Scenario: Recording door lock actuation history, seat position presets, and lighting profiles in vehicle BCMs. IC Role / Device Role / Timing Role: SPI EEPROM storing user-configurable parameters with hardware WP pin tied to ignition signal for safety locking. Use Value: Meets AEC-Q100 stress requirements and supports diagnostic traceability without compromising functional safety. |
Use Scenario: Saving patient-specific therapy parameters and device calibration logs in portable ECG monitors. IC Role / Device Role / Timing Role: Secure, tamper-resistant memory accessed only during authorized service mode via controlled SPI commands. Use Value: Complies with IEC 62304 data integrity requirements and maintains audit trail for regulatory reporting. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95128-WMN6TP | 128 Kbit capacity, 20 MHz max clock at 5 V, same 1.8–5.5 V range, TSSOP-8 package, but lacks HOLD pin. | Higher density suitable for larger configuration sets; absence of HOLD limits use in multi-device SPI arbitration. | Select when >1 Kbit storage is needed and HOLD functionality is not required in the system architecture. |
| CAT25010VI-GT3 | 1 Kbit, 10 MHz max clock at 1.8 V, TSSOP-8, identical pinout and instruction set, but rated only to +85°C (no extended temp option). | Lower speed at 1.8 V reduces throughput in low-voltage designs; same industrial temp grade but no automotive qualification path. | Choose for cost-sensitive consumer applications where 10 MHz suffices and extended temperature is unnecessary. |
Compared with AT25010AN-10SU-1.8-T, M95128-WMN6TP offers greater density but sacrifices HOLD functionality critical for bus arbitration, while CAT25010VI-GT3 matches pinout and function but trades off maximum clock rate and lacks automotive-grade validation.
Availability
AT25010AN-10SU-1.8-T is available at Aetrix Electronics and suitable for industrial automation controllers, medical diagnostics equipment, and automotive body electronics requiring stable component supply, long-term data retention, and 1.8 V compatibility.
Supply support for AT25010AN-10SU-1.8-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains its legacy serial EEPROM portfolio with full technical documentation, longevity commitments, and industrial-grade reliability validation.
The AT25010A family was designed specifically for low-voltage, low-power embedded systems needing SPI-compatible nonvolatile memory with hardware write protection and robust endurance-targeting industrial, medical, and automotive subsystems.
FAQ
What is the maximum clock frequency supported by AT25010AN-10SU-1.8-T at 1.8 V?
The AT25010AN-10SU-1.8-T supports up to 5 MHz at 1.8 V, as specified in Table 4 AC Characteristics under "1.8–5.5 V" column for fSCK. This ensures reliable SPI communication in ultra-low-power systems while maintaining timing margins for noise immunity and board-level signal integrity.
Does AT25010AN-10SU-1.8-T require an external erase cycle before writing?
No, AT25010AN-10SU-1.8-T does not require a separate erase cycle. All write operations are self-timed and automatically erase and program the target location within the ≤5 ms write cycle. This simplifies firmware design and eliminates erase-related timing overhead.
How is write protection implemented on AT25010AN-10SU-1.8-T?
AT25010AN-10SU-1.8-T implements dual-layer write protection: hardware via the WP pin (low disables all writes instantly), and software via the status register's BP1/BP0 bits, which configure 1/4, 1/2, or full-array block protection. Both layers must be satisfied for successful writes.
Can AT25010AN-10SU-1.8-T operate in SPI Mode 3 (CPOL=1, CPHA=1)?
Yes, AT25010AN-10SU-1.8-T explicitly supports SPI Modes 0 and 3, as stated in the Features section. In Mode 3, data is sampled on the falling edge of SCK and changed on the rising edge, enabling interoperability with controllers configured for inverted clock polarity and phase.
What is the purpose of the HOLD pin on AT25010AN-10SU-1.8-T?
The HOLD pin on AT25010AN-10SU-1.8-T suspends ongoing SPI communication without resetting the internal address counter or instruction state. When asserted low while SCK is low, it pauses data transfer; releasing HOLD resumes exactly where it left off - essential for multi-master arbitration and deterministic timing control.
AT25010AN-10SU-1.8-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25010AN-10SU-1.8-T FAQ
1.How can I place an order for AT25010AN-10SU-1.8-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25010AN-10SU-1.8-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25010AN-10SU-1.8-T reliable?
The price and inventory of AT25010AN-10SU-1.8-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25010AN-10SU-1.8-T is usually 5 days.
3.What payment methods are accepted for AT25010AN-10SU-1.8-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25010AN-10SU-1.8-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25010AN-10SU-1.8-T?
AT25010AN-10SU-1.8-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25010AN-10SU-1.8-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25010AN-10SU-1.8-T?
For technical support, including AT25010AN-10SU-1.8-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25010AN-10SU-1.8-T requirements.
6.How does Aetrix verify that AT25010AN-10SU-1.8-T is sourced from the original manufacturer or authorized distributors?
All AT25010AN-10SU-1.8-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25010AN-10SU-1.8-T meets industry standards.
7.What is the process for return or replacement of AT25010AN-10SU-1.8-T?
All AT25010AN-10SU-1.8-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25010AN-10SU-1.8-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25010AN-10SU-1.8-T part is unused and in its original packaging.
Return procedure for AT25010AN-10SU-1.8-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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