Microchip Technology AT25010B-MAHL-T
- Part No.:
- AT25010B-MAHL-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT25010B-MAHL-T.pdf
- Description:
- IC EEPROM 1KBIT SPI 20MHZ 8UDFN
- Quantity:
- Payment:

- Shipping:

Inventory:5,000
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Product details
Overview
AT25010B-MAHL-T from Microchip Technology is a 1 Kbit (128 × 8) SPI Serial EEPROM with 1.8–5.5 V operation, 20 MHz max clock rate at 5 V, industrial temperature range (−40°C to +85°C), and hardware/software write protection. It serves as nonvolatile configuration storage in microcontroller-based embedded systems requiring reliable, low-power data retention.
For engineers reviewing the AT25010B-MAHL-T datasheet, AT25010B-MAHL-T pinout, AT25010B-MAHL-T application, or AT25010B-MAHL-T equivalent, key selection considerations include its 8-pin SOIC package, SPI Mode 0/3 compatibility, 5 ms max self-timed write cycle, 1 M write endurance, and block-level write protection via STATUS register and WP pin.
Technical Context
The AT25010B-MAHL-T implements a synchronous SPI slave interface with fixed MSB-first serial protocol, supporting both Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 1). Data latching occurs on SCK rising edge; output transitions occur on falling edge.
It integrates an 8-bit STATUS register controlling write enable (WEL), ready/busy (RDY/BSY), and block protection (BP1/BP0), plus dedicated hardware pins (WP, HOLD) for real-time write inhibition and serial communication suspension without reset. Internal high-voltage generation enables byte/page writes without external charge pumps.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1,024 bits (128 words × 8 bits); sufficient for firmware flags, calibration data, or small configuration tables. |
| Supply Voltage Range | 1.8 V to 5.5 V; enables direct interfacing with 1.8 V, 3.3 V, and 5 V logic domains without level shifters. |
| Max Clock Frequency | 20 MHz at VCC ≥ 4.5 V; supports fast read/write transfers in time-critical boot or logging sequences. |
| Write Cycle Time | ≤5 ms maximum; deterministic erase-and-program timing simplifies host polling and timeout handling. |
| Endurance & Retention | 1,000,000 write cycles / 100 years data retention at 55°C; meets long-life requirements for industrial controllers and medical devices. |
| Operating Temperature | −40°C to +85°C; qualified for use in automotive body electronics, industrial sensors, and outdoor IoT nodes. |
| ESD Protection | >4,000 V HBM; reduces need for external ESD protection in board-level designs. |
Pinout & Package
AT25010B-MAHL-T is housed in an 8-lead SOIC package (3.9 mm × 4.9 mm, 1.27 mm pitch), compatible with standard surface-mount assembly processes and legacy PCB footprints.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable; must be driven low before SCK toggling; requires pull-up resistor (≤10 kΩ) tied to VCC for robust power-up behavior. |
| SO | Serial Data Output | Tri-state output; drives data on falling edge of SCK; enters high-impedance state when CS is high or HOLD is asserted. |
| WP | Write-Protect | Hardware lock: pulls low to inhibit all write commands (WREN, WRITE, WRSR); does not interrupt ongoing internal write cycles. |
| GND | Ground Reference | System ground return path for VCC and all I/O signals; must be low-impedance connection to minimize noise coupling. |
| SI | Serial Data Input | Receives opcodes, addresses, and data on rising edge of SCK; MSB-first; ignored during HOLD or when CS is high. |
| SCK | Serial Clock Input | Master-generated clock; defines timing for SI sampling (rising edge) and SO output (falling edge); idle polarity depends on SPI mode. |
| HOLD | Suspend Control | Pauses serial transfer mid-sequence when asserted low during SCK low; preserves internal state; no effect on active write cycles. |
| VCC | Power Supply | 1.8–5.5 V input; must ramp monotonically at ≤0.1 V/µs; POR circuit ensures stable initialization before accepting commands. |
Key Features
| Feature | Design Value |
|---|---|
| 8-byte page write mode | Enables burst programming of up to 8 bytes per write command, reducing total transaction overhead vs. byte-wise writes. |
| Block write protection (BP1/BP0) | Configurable via STATUS register to protect 0%, 25%, 50%, or 100% of memory array-prevents accidental overwrites of critical firmware sections. |
| Dual write protection layer | Combines hardware (WP pin) and software (WREN + STATUS register) mechanisms for fail-safe data integrity in safety-critical applications. |
| Hold function with zero-cycle resume | Allows master to pause ongoing reads/writes without losing context or requiring reinitialization-ideal for interrupt-driven MCU environments. |
| Green RoHS-compliant packaging | Lead-free, halide-free SOIC construction meets global environmental compliance mandates without performance trade-offs. |
Applications
| Industrial Sensor Calibration Storage | Medical Device Configuration Backup |
|---|---|
|
Use Scenario: Storing factory-calibrated sensor offset/gain coefficients and user-adjusted thresholds in a battery-powered environmental monitor. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed during power-on initialization and periodic recalibration routines. Use Value: Ensures measurement accuracy across device lifetime using 100-year data retention and 1M-cycle endurance under field update conditions. |
Use Scenario: Retaining patient-specific therapy parameters and device usage logs in a portable infusion pump with USB reprogramming capability. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store isolated from main MCU flash via hardware WP pin and STATUS register locking. Use Value: Prevents unintended parameter corruption during hot-plug USB events using dual-layer (hardware + software) write protection. |
| Automotive Body Control Module Settings | Smart Home Gateway Firmware Flags |
|
Use Scenario: Saving seat/mirror position presets and lighting profiles in a vehicle's door module operating across −40°C to +85°C ambient. IC Role / Device Role / Timing Role: Low-voltage (1.8 V) EEPROM interfaced directly to 3.3 V MCU SPI bus, eliminating level-shifting components. Use Value: Guarantees reliable operation at cold cranking voltages and extended thermal cycling due to industrial-grade qualification and 5 ms max write timing. |
Use Scenario: Storing OTA update status flags, network credentials, and user preferences in a Wi-Fi-enabled smart thermostat with intermittent power. IC Role / Device Role / Timing Role: Fast-read (20 MHz) configuration store enabling sub-100 ms boot sequence after brownout recovery. Use Value: Accelerates system readiness using high-speed SPI access and deterministic 5 ms write completion for critical state updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95010-WMN6TP | Same 1 Kbit density, 8-lead SOIC, but rated only to +70°C; max clock 10 MHz at 2.5–5.5 V; no HOLD pin. | Lacks HOLD functionality and industrial temp range; suitable only for commercial-grade consumer electronics. | Select when cost sensitivity outweighs need for hold capability or extended temperature operation. |
| BR24G01NUX-5TR | I²C interface (not SPI); 1.7–5.5 V; 400 kHz standard / 1 MHz fast-mode; 8-lead USON package (2 mm × 2.5 mm). | Requires I²C-capable MCU; smaller footprint but incompatible bus protocol; no hardware WP or HOLD pins. | Choose for space-constrained designs where I²C is already used and SPI pins are unavailable. |
Compared with M95010-WMN6TP and BR24G01NUX-5TR, the AT25010B-MAHL-T uniquely delivers industrial temperature support, 20 MHz SPI speed, and dual hardware/software write protection in a standard SOIC package-making it optimal for robust embedded control where bus flexibility, timing predictability, and data security are prioritized.
Availability
AT25010B-MAHL-T is available at Aetrix Electronics and suitable for industrial sensor calibration storage, medical device configuration backup, and automotive body control module settings requiring stable component supply across extended temperature ranges and multi-year production cycles.
Supply support for AT25010B-MAHL-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog, FPGA, and memory solutions, with a focus on embedded control and connectivity.
The AT25010B-MAHL-T belongs to Microchip's AT25xxx family of SPI EEPROMs, designed specifically for reliable, low-voltage nonvolatile storage in resource-constrained embedded systems where SPI interface simplicity and industrial-grade reliability are essential.
FAQ
What is the maximum clock frequency supported by the AT25010B-MAHL-T?
The AT25010B-MAHL-T supports up to 20 MHz SCK frequency when VCC is 4.5–5.5 V, 10 MHz at 2.5–5.5 V, and 5 MHz across the full 1.8–5.5 V range. These limits are defined in the AC Characteristics table (DS20006251A, page 10) and ensure timing compliance for setup/hold and output validity across voltage grades. The AT25010B-MAHL-T must operate within these bounds to guarantee reliable read/write transactions.
Does the AT25010B-MAHL-T support SPI Mode 0 and Mode 3 simultaneously?
Yes-the AT25010B-MAHL-T natively supports both SPI Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 1). Data is always latched on the rising edge of SCK and output on the falling edge; the only difference is SCK idle polarity. The AT25010B-MAHL-T automatically adapts to whichever mode the host controller selects, provided the idle state matches before and after CS assertion.
How does the Write-Protect (WP) pin interact with ongoing write operations on the AT25010B-MAHL-T?
When WP is pulled low while CS is active, the AT25010B-MAHL-T immediately inhibits further instruction acceptance-including WREN, WRITE, and WRSR-but does not abort an internal write cycle already in progress. If the AT25010B-MAHL-T has entered the self-timed 5 ms write phase, WP assertion has no effect until completion. This behavior is documented in Section 2.3 and Figure 5-3 of DS20006251A.
Can the AT25010B-MAHL-T be used in a 1.8 V system without level shifters?
Yes-the AT25010B-MAHL-T is fully specified for 1.8 V operation, including DC characteristics (ISB1 = 0.1–0.5 µA standby current), AC timing (5 MHz SCK max), and logic thresholds (VIL ≤ 0.3×VCC, VIH ≥ 0.7×VCC). Its 1.8–5.5 V supply range allows direct connection to 1.8 V MCUs without external level translation, as confirmed in Table 4-1 and Table 4-2 of the datasheet.
What is the default state of the STATUS register after power-up for the AT25010B-MAHL-T?
At power-up, the AT25010B-MAHL-T defaults to Standby mode with WEL = 0 (write disabled), RDY/BSY = 0 (ready), and BP1/BP0 unchanged from their last written value (nonvolatile). The EEPROM array is shipped with all FFh data. This behavior is explicitly defined in Section 4.6.5 and 4.6.6 of DS20006251A, ensuring predictable initialization without host-side register initialization overhead.
AT25010B-MAHL-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT25010B-MAHL-T FAQ
1.How can I place an order for AT25010B-MAHL-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25010B-MAHL-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25010B-MAHL-T reliable?
The price and inventory of AT25010B-MAHL-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25010B-MAHL-T is usually 5 days.
3.What payment methods are accepted for AT25010B-MAHL-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25010B-MAHL-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25010B-MAHL-T?
AT25010B-MAHL-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25010B-MAHL-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25010B-MAHL-T?
For technical support, including AT25010B-MAHL-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25010B-MAHL-T requirements.
6.How does Aetrix verify that AT25010B-MAHL-T is sourced from the original manufacturer or authorized distributors?
All AT25010B-MAHL-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25010B-MAHL-T meets industry standards.
7.What is the process for return or replacement of AT25010B-MAHL-T?
All AT25010B-MAHL-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25010B-MAHL-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25010B-MAHL-T part is unused and in its original packaging.
Return procedure for AT25010B-MAHL-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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