Microchip Technology AT25020B-XHL-B
- Part No.:
- AT25020B-XHL-B
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT25020B-XHL-B.pdf
- Description:
- IC EEPROM 2KBIT SPI 20MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:960
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Product details
Overview
AT25020B-XHL-B from Microchip Technology is a 2 Kbit (256 × 8) SPI Serial EEPROM with industrial-grade operation (−40°C to +85°C), 1.8–5.5 V supply range, and 20 MHz max clock rate at 5 V. It features hardware write protection via WP pin, HOLD suspend functionality, and 8-byte page write mode - deployed in embedded control systems for firmware parameter storage and calibration data retention.
For engineers reviewing the AT25020B-XHL-B datasheet, AT25020B-XHL-B pinout, AT25020B-XHL-B application, or AT25020B-XHL-B equivalent, key selection considerations include SPI Mode 0/3 compatibility, 5 ms max self-timed write cycle, block-level write protection (1/4, 1/2, or full array), and RoHS-compliant 8-lead TSSOP packaging with validated 8-pin functional mapping.
Technical Context
The AT25020B-XHL-B implements a synchronous SPI slave interface with fixed MSB-first data framing, rising-edge input sampling on SI, and falling-edge output latching on SO. Its internal architecture includes a STATUS register with nonvolatile BP1/BP0 bits for persistent block protection configuration and a WEL latch controlling write enable state.
It supports dual SPI modes (0 and 3) differentiated only by SCK idle polarity; both require CS assertion before SCK activity and enforce strict timing windows for tSU, tH, tCSS, and tCSH. The HOLD pin suspends serial communication without resetting the instruction sequence, while WP provides hardware-level write inhibition independent of STATUS register settings.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 2 Kbit (256 words × 8 bits); sufficient for bootloader config, sensor calibration tables, or device ID storage |
| Supply voltage | 1.8 V to 5.5 V; enables direct interfacing with 1.8 V, 3.3 V, and 5 V microcontrollers without level shifting |
| Max clock frequency | 20 MHz at 4.5–5.5 V; supports high-throughput firmware updates in resource-constrained systems |
| Write cycle time | ≤5 ms maximum; deterministic erase/write latency critical for real-time logging and fail-safe parameter saves |
| Endurance & retention | 1,000,000 write cycles / 100 years data retention at 55°C; meets long-life requirements in industrial controllers |
| Operating temperature | −40°C to +85°C; qualified for deployment in automotive body electronics and factory automation modules |
| ESD protection | >4 kV HBM; robust against handling and board-level electrostatic discharge in production environments |
Pinout & Package
AT25020B-XHL-B is packaged in an 8-lead TSSOP (Thin Shrink Small Outline Package) with 0.65 mm lead pitch and exposed pad (GND-connected or floating per design). Pin functions are electrically identical across SOIC/TSSOP/UDFN/VFBGA variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be low before SCK starts and held stable during transaction; pull-up resistor (≤10 kΩ) recommended for power-up robustness |
| SO | Serial Data Output | Tri-state output; drives data on falling edge of SCK; high-impedance when CS high or HOLD active |
| WP | Write-Protect | Hardware lock: low = all write operations inhibited; overrides software write-enable state; no effect once internal write cycle begins |
| GND | Ground reference | System ground connection; exposed pad may be tied to GND for thermal and EMI performance |
| SI | Serial Data Input | Receives opcodes, addresses, and data on rising edge of SCK; MSB-first; ignored during HOLD or CS high |
| SCK | Serial Clock | Master-generated clock; defines SPI mode via idle polarity (Mode 0 = low idle, Mode 3 = high idle) |
| HOLD | Suspend Serial Input | Pauses ongoing SPI transfer without resetting state; requires SCK low to assert/deassert; SO goes high-Z immediately |
| VCC | Power supply | 1.8–5.5 V input; must ramp monotonically at ≤0.1 V/µs; POR circuit enforces 100 µs delay before first command |
Key Features
| Feature | Design Value |
|---|---|
| 8-byte page write mode | Reduces write overhead by enabling up to 8 bytes per WRITE command, cutting total I/O transactions by 8× vs byte-write |
| Block write protection | Nonvolatile BP1/BP0 bits allow permanent 1/4, 1/2, or full memory array lock - prevents accidental firmware corruption |
| Hardware + software write protection | Combines WP pin (instant hardware disable) with WREN/WRDI instructions and STATUS register control for layered security |
| HOLD pin suspend function | Enables multi-master arbitration or CPU context switching without losing SPI state - eliminates re-initialization delays |
| Green package compliance | RoHS, halide-free, and lead-free construction meets IPC/JEDEC J-STD-020D reflow and environmental compliance mandates |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Nonvolatile parameter repository accessed via SPI during boot and runtime; write-protected during normal operation using BP bits. Use Value: Ensures deterministic startup behavior and immunity to power-loss-induced corruption due to 5 ms max write cycle and 1M endurance. |
Use Scenario: Retaining sensor offset/gain coefficients and regulatory audit logs in portable diagnostic equipment requiring FDA 21 CFR Part 11 compliance. IC Role / Device Role / Timing Role: Secure, tamper-resistant memory for calibrated values; WP pin physically disabled during field service to prevent unauthorized writes. Use Value: 100-year data retention guarantees traceability over product lifetime; ESD >4 kV protects against clinical handling events. |
| Automotive Body Control Module | Smart Energy Meter Firmware Settings |
|
Use Scenario: Saving seat/mirror position presets, lighting profiles, and CAN node configuration in 12 V automotive subsystems with wide input transients. IC Role / Device Role / Timing Role: Low-voltage EEPROM interfaced directly to 3.3 V MCU; operates reliably across −40°C to +85°C ambient with no external regulators. Use Value: 1.8 V minimum VCC allows seamless integration with modern low-power MCUs; TSSOP package withstands automotive thermal cycling. |
Use Scenario: Holding tariff schedules, metering constants, and firmware update flags in utility-grade electricity meters deployed in outdoor enclosures. IC Role / Device Role / Timing Role: Trusted configuration store with hardware write lock (WP) enabled during metrology certification; STATUS register used for field diagnostics. Use Value: Block protection prevents unauthorized tariff changes; 20 MHz SPI speed enables rapid firmware patch loading during remote updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95256-DFMN6TP | 256 Kbit capacity, same 1.8–5.5 V range and TSSOP-8 package; supports 20 MHz at 5 V but lacks HOLD pin | Higher density for complex configuration sets; unsuitable where suspend functionality is required for multi-tasking hosts | Select when memory expansion is needed and HOLD is unused; verify absence of HOLD does not impact system arbitration logic |
| CAT25256YI-GT3 | 256 Kbit, 1.8–5.5 V, TSSOP-8; includes software reset command and enhanced write-protection granularity (sector-level) | Better suited for firmware-over-the-air (FOTA) updates requiring fine-grained protection; no hardware WP/HOLD pins | Choose for cloud-connected devices needing secure sector locking; avoid if hardware-level WP lockout is mandated by safety standards |
Compared with M95256-DFMN6TP and CAT25256YI-GT3, the AT25020B-XHL-B offers optimal balance of proven reliability, hardware-controlled write safety (WP + HOLD), and minimal footprint for cost-sensitive 2 Kbit use cases - making it preferred for legacy-compatible designs where pin count and deterministic timing are prioritized over density.
Availability
AT25020B-XHL-B is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, and automotive body electronics requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for AT25020B-XHL-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, analog, FPGA, and memory solutions, headquartered in Chandler, Arizona, with global manufacturing and support infrastructure.
The AT25020B-XHL-B belongs to Microchip's AT25xxx family of SPI EEPROMs, designed specifically for reliable, low-voltage nonvolatile storage in space-constrained embedded systems where data integrity and long-term retention are critical.
FAQ
What is the maximum clock frequency supported by the AT25020B-XHL-B at 3.3 V operation?
The AT25020B-XHL-B supports up to 10 MHz SCK frequency when VCC is between 2.5 V and 5.5 V - covering standard 3.3 V operation. This is specified in Table 4-3 of the DS20006251A datasheet under AC Characteristics. At 1.8 V, the limit drops to 5 MHz. The AT25020B-XHL-B must not exceed these rates to ensure setup/hold timing compliance and reliable opcode decoding.
Does the AT25020B-XHL-B support SPI Mode 1 or Mode 2?
No, the AT25020B-XHL-B explicitly supports only SPI Modes 0 and 3, as confirmed in the Features section and Section 5.1 of the datasheet. These modes share identical data sampling (rising edge for input, falling edge for output) but differ in SCK idle polarity. Modes 1 and 2 - which sample on opposite edges - are not compatible with the AT25020B-XHL-B's internal timing architecture.
How does the Write-Protect (WP) pin interact with the STATUS register's BP bits?
The WP pin provides hardware-level write inhibition that takes immediate precedence over software-configured BP bits in the STATUS register. When WP is low, all write operations (including WRSR) are blocked regardless of BP1/BP0 state. However, if WP is high, the BP bits determine which memory regions are protected. The AT25020B-XHL-B thus implements a two-tier protection scheme: physical lock (WP) and logical lock (BP).
Can the HOLD pin pause an ongoing write cycle in the AT25020B-XHL-B?
No, the HOLD pin cannot pause an internal write cycle once initiated. As stated in Section 5.3, "the Hold mode, however, does not have an effect on the internal write cycle." HOLD only suspends serial communication (SI/SO/SCK interaction) while CS remains asserted. If a WRITE command has already triggered the self-timed 5 ms erase/write sequence, HOLD has no influence - the AT25020B-XHL-B will complete it autonomously.
What is the default state of the STATUS register after power-up for the AT25020B-XHL-B?
At power-up, the AT25020B-XHL-B initializes with WEL = 0 (write disabled), RDY/BSY = 0 (ready), and BP1/BP0 unchanged from their last written state (nonvolatile). The EEPROM array itself ships with all locations set to 0xFF. This default ensures no unintended writes occur on boot, and the AT25020B-XHL-B enters standby mode until CS is asserted and WREN is issued.
AT25020B-XHL-B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT25020B-XHL-B FAQ
1.How can I place an order for AT25020B-XHL-B through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25020B-XHL-B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25020B-XHL-B reliable?
The price and inventory of AT25020B-XHL-B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25020B-XHL-B is usually 5 days.
3.What payment methods are accepted for AT25020B-XHL-B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25020B-XHL-B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25020B-XHL-B?
AT25020B-XHL-B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25020B-XHL-B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25020B-XHL-B?
For technical support, including AT25020B-XHL-B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25020B-XHL-B requirements.
6.How does Aetrix verify that AT25020B-XHL-B is sourced from the original manufacturer or authorized distributors?
All AT25020B-XHL-B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25020B-XHL-B meets industry standards.
7.What is the process for return or replacement of AT25020B-XHL-B?
All AT25020B-XHL-B units undergo pre-shipment inspection (PSI). If there is an issue with AT25020B-XHL-B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25020B-XHL-B part is unused and in its original packaging.
Return procedure for AT25020B-XHL-B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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