Microchip Technology AT25020N-10SI-2.7
- Part No.:
- AT25020N-10SI-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25020N-10SI-2.7.pdf
- Description:
- IC EEPROM 2KBIT SPI 3MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,472
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25020N-10SI-2.7 from Atmel (now Microchip) is a 2-kbit SPI serial EEPROM organized as 256 words × 8 bits, operating from 2.7V to 5.5V, supporting 3.0 MHz clock rate at 5V, with 8-byte page write capability and hardware/software write protection for industrial embedded systems requiring nonvolatile data storage.
For engineers reviewing the AT25020N-10SI-2.7 datasheet, AT25020N-10SI-2.7 pinout, AT25020N-10SI-2.7 application, or AT25020N-10SI-2.7 equivalent, key selection considerations include SPI Mode 0/3 compatibility, 10 ms max self-timed write cycle, block-level write protection (1/4, 1/2, or full array), HOLD/CS-controlled serial suspension, and JEDEC SOIC-8 packaging for space-constrained PCBs.
Technical Context
The AT25020N-10SI-2.7 implements a synchronous slave SPI interface with separate SI/SO pins, MSB-first data transfer, and op-code–driven instruction set (WREN, WRITE, READ, RDSR, WRSR). It uses an 8-bit instruction register and requires CS low-to-high transition to initiate internal write cycles.
Its status register (BP1/BP0/WEN/RDY bits) controls nonvolatile block protection and write enable state; protection levels map directly to memory address ranges (e.g., BP1=1, BP0=0 protects addresses 0x80–0xFF for AT25020). The HOLD pin suspends ongoing communication without resetting the sequence when asserted low during SCK low time.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2048 bits (256 × 8-bit words) - fixed address space usable for configuration storage or calibration data. |
| Supply Voltage | 2.7V to 5.5V - supports single-supply operation across industrial and mixed-voltage systems. |
| Max Clock Rate | 3.0 MHz at VCC = 5.0V - enables fast read/write throughput in high-speed microcontroller interfaces. |
| Write Cycle Time | 10 ms maximum - deterministic self-timed programming eliminates external timing control overhead. |
| Endurance | 1 million write cycles - suitable for frequent parameter updates in field-deployed equipment. |
| Data Retention | 100 years - ensures long-term reliability of stored settings without refresh. |
| Operating Temp | -40°C to +85°C - qualified for industrial ambient environments without derating. |
Pinout & Package
AT25020N-10SI-2.7 is housed in an 8-lead JEDEC SOIC package (0.150" wide body, 1.27 mm pitch), compliant with MS-012 standard, with gull-wing leads optimized for surface-mount reflow assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be low to accept instructions and data on SI/SCK; high impedance on SO when high. |
| SCK | Serial Clock | Input-only clock input; defines timing for SI sampling and SO output; supports SPI Modes 0 and 3. |
| SI | Serial Data Input | Master-to-slave data path for op-codes, addresses, and write data; MSB-first transmission required. |
| SO | Serial Data Output | Slave-to-master data path for read data and status register bits; tri-stated when CS is high. |
| GND | Ground Reference | Primary return path for VCC and all I/O signals; must be low-impedance for noise immunity. |
| VCC | Power Supply | Single supply input (2.7–5.5V); powers internal logic and memory array; decoupling capacitor recommended. |
| WP | Write Protect | Hardware lock: low disables all write operations regardless of status register or WREN state. |
| HOLD | Communication Suspend | Pauses active SPI transaction without resetting address counter; requires SCK low during assertion. |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode 0/3 Compatibility | Interoperates with 68HC11, AVR, PIC, and ARM-based MCUs without protocol translation logic. |
| 8-byte Page Write | Reduces total write time by up to 8× vs. byte-write mode; improves firmware update efficiency. |
| Nonvolatile Block Protection | BP1/BP0 bits in status register permanently configure 1/4, 1/2, or full-array write lock without external components. |
| HOLD Pin Functionality | Enables multi-master arbitration or CPU interrupt handling without losing serial context or requiring re-initialization. |
| Self-timed Write Cycle | Eliminates need for external delay timers or polling loops; simplifies host firmware design. |
Applications
| Industrial Sensor Calibration Storage | Medical Device Configuration Memory |
|---|---|
Use Scenario: Storing factory-calibrated offset/gain coefficients and sensor linearization tables in temperature/humidity transmitters. IC Role / Device Role / Timing Role: Nonvolatile configuration store accessed during power-up initialization and runtime correction lookups via SPI. Use Value: Enables traceable, field-updatable calibration without requiring external FRAM or battery-backed SRAM. | Use Scenario: Holding user-selectable therapy parameters, device ID, and usage logs in portable infusion pumps. IC Role / Device Role / Timing Role: Secure, low-power persistent memory for safety-critical settings with hardware WP pin lockdown. Use Value: Meets IEC 62304 Class B software requirements through deterministic 10 ms writes and 1M-cycle endurance. |
| Automotive Body Control Module (BCM) | Smart Energy Meter Firmware Patch Storage |
Use Scenario: Saving seat/mirror position presets, lighting profiles, and diagnostic fault codes in 12V automotive BCMs. IC Role / Device Role / Timing Role: SPI-connected EEPROM interfacing with 8-bit/16-bit automotive MCUs under -40°C to +85°C conditions. Use Value: Qualified for automotive industrial temp range with 100-year retention-avoids recalibration after vehicle battery disconnect. | Use Scenario: Storing firmware patch binaries and cryptographic keys for secure over-the-air (OTA) updates in utility meters. IC Role / Device Role / Timing Role: Trusted nonvolatile storage for signed code segments, accessed only during verified boot sequences. Use Value: Hardware write protection (WP pin + status register) prevents unauthorized modification of critical OTA payload storage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95256-DRMN6TP/K | 256 Kbit capacity, 20 MHz max clock, 5 ms write cycle, same SOIC-8 package and SPI Mode 0/3 interface. | Higher density and speed suit firmware logging; not drop-in due to larger memory map and different status register layout. | Select when >2 Kbit storage or faster write throughput is required; verify address decoding and timing margins. |
| 25AA020A-I/SN | 2 Kbit, same SOIC-8, 10 ms write cycle, but supports 1.8V–5.5V operation and includes unique 128-bit ID. | Broader voltage range and factory-programmed ID support secure device authentication in IoT nodes. | Prefer for battery-powered or security-sensitive designs where 1.8V compatibility or hardware identity is mandatory. |
Compared with M95256-DRMN6TP/K and 25AA020A-I/SN, AT25020N-10SI-2.7 offers optimal balance of proven industrial reliability, minimal footprint, and deterministic 10 ms writes-making it ideal for cost-sensitive, space-constrained embedded systems where 2 Kbit suffices and 2.7V minimum supply is acceptable.
Availability
AT25020N-10SI-2.7 is available at Aetrix Electronics and suitable for industrial sensor nodes, medical diagnostics equipment, automotive body controllers, and smart metering systems requiring stable component supply across extended product lifecycles.
Supply support for AT25020N-10SI-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology (formerly Atmel) is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions for industrial, automotive, and consumer markets.
The AT250xx family was designed specifically for SPI-based embedded systems needing reliable, low-voltage serial EEPROM with hardware data protection and compact packaging-targeting applications where board space, power budget, and long-term data integrity are critical.
FAQ
What is the memory organization of the AT25020N-10SI-2.7?
The AT25020N-10SI-2.7 contains 2048 bits of serial EEPROM organized as 256 words × 8 bits, with a linear address space from 0x00 to 0xFF. Each word is accessed individually during READ or WRITE operations, and the 8-byte page write mode allows sequential programming within aligned 8-byte boundaries without address rollover.
Does the AT25020N-10SI-2.7 support both SPI Mode 0 and Mode 3?
Yes, the AT25020N-10SI-2.7 explicitly supports SPI Modes 0 (CPOL=0, CPHA=0) and 3 (CPOL=1, CPHA=1), enabling direct interoperability with common microcontrollers including the 68HC11, AVR, and PIC families. The device operates as a slave with SCK as input-only, and timing complies with JEDEC-standard AC characteristics for both modes.
How does hardware write protection work on the AT25020N-10SI-2.7?
Hardware write protection on the AT25020N-10SI-2.7 is implemented via the dedicated WP (Write Protect) pin: when pulled low, it inhibits all write operations-including WREN, WRITE, and WRSR-regardless of the status register's BP1/BP0 or WEN bits. This provides fail-safe protection against accidental or malicious writes during power transitions or firmware faults.
What is the purpose of the HOLD pin on the AT25020N-10SI-2.7?
The HOLD pin on the AT25020N-10SI-2.7 allows a master device to temporarily suspend an ongoing SPI transaction without resetting the internal address counter or command state. When asserted low during SCK low time, it places SO in high-impedance and ignores SI inputs; resuming requires bringing HOLD high while SCK remains low.
Can the AT25020N-10SI-2.7 be used in automotive applications?
The AT25020N-10SI-2.7 is rated for industrial temperature range (-40°C to +85°C) and is not AEC-Q200 qualified. While it may function in some automotive cabin environments, Microchip offers automotive-grade variants (e.g., AT25020AN-10SI-2.7) with extended qualification. For production automotive use, consult Microchip's official automotive product roadmap before selecting AT25020N-10SI-2.7.
AT25020N-10SI-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 3 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25020N-10SI-2.7 FAQ
1.How can I place an order for AT25020N-10SI-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25020N-10SI-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25020N-10SI-2.7 reliable?
The price and inventory of AT25020N-10SI-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25020N-10SI-2.7 is usually 5 days.
3.What payment methods are accepted for AT25020N-10SI-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25020N-10SI-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25020N-10SI-2.7?
AT25020N-10SI-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25020N-10SI-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25020N-10SI-2.7?
For technical support, including AT25020N-10SI-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25020N-10SI-2.7 requirements.
6.How does Aetrix verify that AT25020N-10SI-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25020N-10SI-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25020N-10SI-2.7 meets industry standards.
7.What is the process for return or replacement of AT25020N-10SI-2.7?
All AT25020N-10SI-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25020N-10SI-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25020N-10SI-2.7 part is unused and in its original packaging.
Return procedure for AT25020N-10SI-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25020N-10SI-2.7 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
