Microchip Technology AT25040A-10PU-2.7
- Part No.:
- AT25040A-10PU-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT25040A-10PU-2.7.pdf
- Description:
- IC EEPROM 4KBIT SPI 20MHZ 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,924
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Product details
Overview
AT25040A-10PU-2.7 from Microchip Technology (formerly Atmel) is a 4-kbit SPI serial EEPROM organized as 512 words × 8 bits, operating from 2.7V to 5.5V with 20 MHz max clock rate at 5V, 8-byte page write capability, and hardware/software write protection. It serves as nonvolatile configuration storage in microcontroller-based industrial control modules requiring low-power, reliable data retention.
For engineers reviewing the AT25040A-10PU-2.7 datasheet, AT25040A-10PU-2.7 pinout, AT25040A-10PU-2.7 application, or AT25040A-10PU-2.7 equivalent, this page delivers verified electrical specs, JEDEC PDIP-8 package details, SPI Mode 0/3 timing compliance, block write protection mapping, and real-world use cases for embedded system designers.
Technical Context
The AT25040A-10PU-2.7 implements a synchronous slave SPI interface with dedicated SI/SO pins, CS-driven selection, and HOLD/ WP control lines. Its internal architecture includes an 8-bit instruction register, status register with BP1/BP0 block protection bits, and self-timed write cycle logic that eliminates external erase commands.
It supports two SPI modes (0 and 3), operates across industrial temperature (−40°C to +85°C), and features dual write-protection mechanisms: hardware via the WP pin and software via WRSR-configurable BP bits enabling 0%, 25%, 50%, or 100% array protection - all validated for 1 million write cycles and 100-year data retention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4096 bits (512 × 8), sufficient for firmware calibration tables or device ID storage in compact MCU systems |
| Supply Voltage Range | 2.7V to 5.5V - enables direct interfacing with 3.3V and 5V logic without level-shifting |
| Max Clock Frequency | 20 MHz at VCC = 5V - supports high-throughput configuration loading in time-critical boot sequences |
| Page Write Size | 8 bytes - minimizes write latency per transaction while avoiding overwriting adjacent data during partial updates |
| Write Endurance | 1 million cycles - ensures robustness in field-updatable parameter logging applications |
| Data Retention | 100 years at 25°C - guarantees long-term integrity of stored calibration or security keys |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade deployment in motor drives and sensor nodes |
Pinout & Package
AT25040A-10PU-2.7 uses an 8-lead JEDEC PDIP package (package code 8P3), 0.300" wide body, RoHS-compliant and green-marked ("U"). Pin spacing follows standard 0.100" pitch; leads are gull-wing shaped with 0.014–0.022" width and 0.115–0.150" length.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be low to accept SPI commands; high-Z SO when CS high |
| SCK | Serial Clock | Input-only clock line synchronized to master; defines timing for SI sampling and SO output |
| SI | Serial Data Input | Command/address/data input path; MSB-first protocol; ignored during HOLD or write cycle |
| SO | Serial Data Output | Read data output; tri-stated when CS high or during internal write; no bus contention risk |
| GND | Ground Reference | Primary return path for VCC and I/O; requires low-impedance PCB connection to minimize noise |
| VCC | Power Supply | Single supply input (2.7–5.5V); powers core logic, memory array, and I/O buffers |
| WP | Write Protect | Hardware lock: low disables all writes regardless of WREN/WRSR state; critical for fail-safe operation |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer without resetting address counter; allows priority interrupt handling |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode 0 & 3 Support | Enables interoperability with diverse MCUs including 68HC11, PIC, and ARM Cortex-M families without protocol translation |
| Block Write Protection | Four configurable protection levels (none, 1/4, 1/2, full array) via nonvolatile BP bits - prevents accidental overwrite of critical sectors |
| Self-timed Write Cycle | 5 ms max duration with automatic completion detection; eliminates need for external delay timers or polling overhead |
| Low Standby Current | 0.2 µA typical at 2.7V - extends battery life in always-on IoT edge sensors and portable diagnostics tools |
| HOLD Functionality | Allows mid-transaction suspension for higher-priority tasks (e.g., ADC sampling), resuming from exact byte position |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Memory |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed during power-up and runtime reconfiguration via SPI from host MCU. Use Value: Ensures deterministic startup behavior and retains settings across brownouts; 1M endurance supports frequent field calibration updates. | Use Scenario: Holding sensor offset/gain coefficients and regulatory compliance logs in portable ECG monitors and infusion pumps. IC Role / Device Role / Timing Role: Secure, tamper-resistant data vault with hardware WP pin enabling clinical staff lockout during operation. Use Value: Meets IEC 62304 data integrity requirements; 100-year retention validates long-term patient record traceability. |
| Automotive Body Control Module | Smart Energy Meter Firmware Patch Storage |
Use Scenario: Saving seat/mirror position presets and lighting profiles in automotive BCMs operating across −40°C to +85°C ambient. IC Role / Device Role / Timing Role: SPI slave EEPROM interfaced to 16-bit automotive MCU; accessed during ignition-on initialization. Use Value: Qualified for industrial temp range; 2.7V min VCC ensures reliable operation during cold-cranking voltage dips. | Use Scenario: Storing firmware patch images and cryptographic keys for secure OTA updates in utility-grade smart meters. IC Role / Device Role / Timing Role: Trusted configuration store isolated by WP pin and status-register BP bits to prevent unauthorized modification. Use Value: Dual protection (hardware WP + software BP) satisfies DLMS/COSEM security mandates for remote firmware integrity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95040-DRMN3TP/K | 4-kbit SPI EEPROM, 1.8–5.5V, 20 MHz, TSSOP-8 package; identical memory organization and instruction set | No HOLD pin; relies solely on CS deassertion for communication pause - unsuitable where mid-transfer suspension is required | Select when board space favors TSSOP and HOLD functionality is unused |
| CAT25040VI-GT3 | 4-kbit SPI EEPROM, 1.8–5.5V, 10 MHz max, SOIC-8; includes enhanced ESD protection (4 kV HBM) | Lower max clock rate limits throughput in high-speed boot loaders; lacks BP1/BP0 granularity - only full-array or none protection | Prefer for cost-sensitive consumer designs where ESD robustness outweighs speed and fine-grained protection needs |
Compared with M95040-DRMN3TP/K and CAT25040VI-GT3, the AT25040A-10PU-2.7 uniquely combines HOLD functionality, precise 25%/50% block protection, and PDIP-8 through-hole compatibility - making it optimal for legacy industrial upgrades and prototyping environments requiring mechanical stability and debug flexibility.
Availability
AT25040A-10PU-2.7 is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, automotive body electronics, and smart metering applications requiring stable component supply, long-lifecycle support, and RoHS-compliant through-hole assembly.
Supply support for AT25040A-10PU-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with a focus on embedded control and connectivity.
The AT25040A-10PU-2.7 belongs to Microchip's legacy serial EEPROM product line, designed specifically for reliable, low-voltage nonvolatile storage in resource-constrained embedded systems where SPI simplicity and data integrity are critical.
FAQ
What is the maximum clock frequency supported by the AT25040A-10PU-2.7?
The AT25040A-10PU-2.7 supports up to 20 MHz SCK frequency when VCC = 5.0V, 10 MHz at 2.7–3.6V, and 5 MHz at 1.8–2.6V. These values are specified in Table 4 of the datasheet and reflect guaranteed AC timing margins under load conditions (CL = 30 pF). The AT25040A-10PU-2.7 must operate within these limits to ensure reliable command execution and data validity.
Does the AT25040A-10PU-2.7 require an external erase cycle before writing?
No, the AT25040A-10PU-2.7 does not require a separate erase cycle. All write operations are self-timed and automatically erase and program the target location in a single atomic operation. This simplifies firmware design and eliminates the need for erase-status polling. The AT25040A-10PU-2.7 completes each write within 5 ms maximum, after which the RDY bit in the status register clears.
How is write protection configured on the AT25040A-10PU-2.7?
Write protection on the AT25040A-10PU-2.7 is implemented through two independent mechanisms: hardware via the WP pin (low = full write disable), and software via BP1/BP0 bits in the status register (set using WRSR instruction). The AT25040A-10PU-2.7 supports four protection levels - none, 1/4, 1/2, or full array - as defined in Table 8 of the datasheet.
What package type does the AT25040A-10PU-2.7 use?
The AT25040A-10PU-2.7 uses an 8-lead JEDEC PDIP package (package code 8P3), 0.300" wide body, with RoHS-compliant green molding compound ("U" suffix). Its pinout matches standard PDIP-8 footprints, supporting through-hole prototyping and legacy industrial PCB assemblies.
Can the AT25040A-10PU-2.7 operate at 1.8V?
No, the AT25040A-10PU-2.7 is rated for 2.7V to 5.5V operation only. For 1.8V compatibility, Microchip offers the AT25040A-10PU-1.8 variant. Using the AT25040A-10PU-2.7 below 2.7V violates absolute maximum ratings and may result in unreliable read/write behavior or increased standby current.
AT25040A-10PU-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT25040A-10PU-2.7 FAQ
1.How can I place an order for AT25040A-10PU-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25040A-10PU-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25040A-10PU-2.7 reliable?
The price and inventory of AT25040A-10PU-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25040A-10PU-2.7 is usually 5 days.
3.What payment methods are accepted for AT25040A-10PU-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25040A-10PU-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25040A-10PU-2.7?
AT25040A-10PU-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25040A-10PU-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25040A-10PU-2.7?
For technical support, including AT25040A-10PU-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25040A-10PU-2.7 requirements.
6.How does Aetrix verify that AT25040A-10PU-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25040A-10PU-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25040A-10PU-2.7 meets industry standards.
7.What is the process for return or replacement of AT25040A-10PU-2.7?
All AT25040A-10PU-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25040A-10PU-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25040A-10PU-2.7 part is unused and in its original packaging.
Return procedure for AT25040A-10PU-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25040A-10PU-2.7 Tags

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