My Inquiry
My Account
Microchip Technology AT25040B-MAHL-T
- Part No.:
- AT25040B-MAHL-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT25040B-MAHL-T.pdf
- Description:
- IC EEPROM 4KBIT SPI 20MHZ 8UDFN
- Quantity:
- Payment:
- Shipping:
Inventory:19,366
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25040B-MAHL-T from Microchip Technology is a 4-Kbit SPI Serial EEPROM (512 × 8) with industrial-grade operation (−40°C to +85°C), 1.8V–5.5V supply range, 20 MHz max clock rate at 5V, and hardware/software write protection via WP pin and STATUS register. It serves as nonvolatile configuration storage in microcontroller-based embedded systems requiring reliable, low-power data retention.
For engineers reviewing the AT25040B-MAHL-T datasheet, AT25040B-MAHL-T pinout, AT25040B-MAHL-T application, or AT25040B-MAHL-T equivalent, key selection criteria include its 8-byte page write capability, block-level write protection (1/4, 1/2, or full array), 5 ms max self-timed write cycle, 1M endurance, and 100-year data retention - all validated across SOIC, TSSOP, UDFN, and VFBGA packages.
Technical Context
The AT25040B-MAHL-T implements a synchronous SPI slave interface supporting Modes 0 and 3, with data latched on SCK rising edge and output on falling edge. Its internal architecture includes a high-voltage generation circuit for EEPROM programming, a STATUS register with BP1/BP0 bits for nonvolatile block protection, and dedicated HOLD and WP pins for real-time serial suspension and hardware write inhibition.
It features a power-on reset (POR) circuit ensuring stable initialization, software reset via CS toggling, and default power-up state: standby mode, WEL = 0, RDY/BSY = 0, and factory-default FFh memory content. The device supports byte and page write operations, with polling via RDSR instruction to monitor write completion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4 Kbit (512 words × 8 bits); enables compact firmware parameter storage without external address decoding logic |
| Supply Voltage Range | 1.8V to 5.5V; supports direct interfacing with 1.8V, 3.3V, and 5V microcontrollers without level shifters |
| Max Clock Frequency | 20 MHz at VCC ≥ 4.5V; delivers up to 2.5 MB/s effective read throughput in burst mode |
| Write Cycle Time | ≤5 ms maximum; ensures predictable timing for firmware update sequences and avoids indefinite blocking |
| Endurance & Retention | 1,000,000 write cycles / 100 years data retention at 55°C; meets long-life requirements for industrial logging and calibration storage |
| Operating Temperature | −40°C to +85°C; qualified for deployment in automotive body control modules and industrial PLC I/O interfaces |
| ESD Protection | >4 kV HBM; provides robustness against handling and board-level electrostatic discharge events |
Pinout & Package
AT25040B-MAHL-T is packaged in an 8-lead SOIC (Small Outline Integrated Circuit) with standard JEDEC MS-012AC footprint (5.3 mm × 4.4 mm, 1.27 mm pitch). This RoHS-compliant, green package supports reflow soldering and is compatible with automated PCB assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be driven low before any SPI transaction; requires pull-up resistor (≤10 kΩ) tied to VCC for robust power-up behavior |
| SO | Serial Data Output | Tri-state output delivering MSb-first data on SCK falling edge; enters high-impedance when CS is high or HOLD is asserted |
| WP | Write-Protect | Hardware lock: pulls low to inhibit all write commands (WREN, WRITE, WRSR); overrides software protection during active CS |
| GND | Ground Reference | Primary return path for VCC and all I/O signals; must be connected to system ground plane for noise immunity |
| SI | Serial Data Input | MSb-first input for opcodes, addresses, and data; sampled on SCK rising edge; ignored during HOLD or CS high |
| SCK | Serial Clock Input | Master-generated clock synchronizing all SPI transfers; supports idle-high (Mode 3) or idle-low (Mode 0) polarity |
| HOLD | Serial Suspend | Pauses ongoing SPI transfer without resetting state; requires SCK low to assert/deassert; preserves internal command context |
| VCC | Power Supply | Single 1.8–5.5V supply; internal POR ensures safe initialization; slew rate ≤0.1 V/µs recommended |
Key Features
| Feature | Design Value |
|---|---|
| 8-byte page write mode | Reduces write latency by batching up to 8 bytes per command, minimizing SPI overhead versus byte-wise writes |
| Nonvolatile block protection (BP1/BP0) | Enables permanent, field-programmable partitioning of memory into protected/unprotected zones without external components |
| Dual write protection (WP pin + WRSR) | Provides layered security: hardware lock for fail-safe prevention and software-configurable granularity for flexible firmware updates |
| Self-timed internal write cycle | Eliminates need for external timing control or busy-wait loops beyond STATUS register polling |
| Industrial temperature grade | Validated operation across −40°C to +85°C ambient, enabling use in uncontrolled environments like outdoor sensors and motor drives |
Applications
| Configuration Storage | Firmware Parameter Backup |
|---|---|
Use Scenario: Storing calibrated sensor offsets, communication protocol settings, and user preferences in a battery-powered environmental monitor. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via SPI during boot and runtime; retains values across power cycles. Use Value: Enables zero-battery-loss reconfiguration after brownout, eliminating need for external backup capacitors or supercapacitors. | Use Scenario: Holding bootloader-verified firmware version flags, secure boot keys, and cryptographic counters in a medical infusion pump controller. IC Role / Device Role / Timing Role: Trusted, tamper-resistant storage for critical runtime metadata; accessed only during secure boot and firmware update phases. Use Value: Supports FIPS-aligned secure boot chains by providing write-protected, high-endurance storage for immutable identifiers and counters. |
| Industrial I/O Module Calibration | Automotive Body Control Unit Settings |
Use Scenario: Recording factory-calibrated ADC gain/offset coefficients and channel-specific linearization tables in a programmable logic controller analog input module. IC Role / Device Role / Timing Role: Factory-programmed reference data store; read once at startup and cached in RAM for real-time correction. Use Value: Achieves ±0.1% measurement accuracy over temperature without recalibration, leveraging 100-year data retention. | Use Scenario: Persisting seat position memory, mirror angle presets, and lighting profiles in a vehicle door module. IC Role / Device Role / Timing Role: Low-power, fast-access nonvolatile memory mapped directly to MCU SPI peripheral; updated only on user command. Use Value: Meets automotive AEC-Q100 Class 2 thermal requirements while supporting <100 µA standby current at 1.8V for always-on functionality. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95040-DRMN6TP/K | 4-Kbit SPI EEPROM (512 × 8); identical 1.8–5.5V range and −40°C to +85°C rating; uses same SOIC-8 package but with different marking and traceability scheme | No HOLD pin; lacks suspend functionality - unsuitable for systems requiring mid-transaction pause capability | Select when HOLD is unused and STMicroelectronics supply chain alignment is required |
| BR24G04FJ-WE2 | 4-Kbit SPI EEPROM (512 × 8); supports 1.7–5.5V, −40°C to +105°C; includes built-in write protect via WP pin and STATUS register, but no HOLD pin | Higher temp rating (+105°C) and lower min VCC (1.7V); optimized for extended-temperature automotive cabin modules | Choose for under-hood or high-temp cabin applications where HOLD is not needed and wider voltage margin is beneficial |
Compared with M95040-DRMN6TP/K and BR24G04FJ-WE2, the AT25040B-MAHL-T uniquely combines HOLD functionality, 20 MHz speed at 5V, and Microchip's validated industrial qualification - making it optimal for real-time suspended transactions and legacy design continuity.
Availability
AT25040B-MAHL-T is available at Aetrix Electronics and suitable for industrial control systems, automotive body electronics, and medical device configuration storage requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for AT25040B-MAHL-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, mixed-signal, analog, and Flash-IP solutions, serving industrial, automotive, consumer, and communications markets with vertically integrated silicon and development tools.
The AT25040B-MAHL-T belongs to Microchip's AT25xxx family of SPI Serial EEPROMs, designed specifically for space-constrained, low-power embedded systems needing reliable, pin-efficient nonvolatile storage with hardware-assisted data integrity.
FAQ
What is the maximum clock frequency supported by the AT25040B-MAHL-T?
The AT25040B-MAHL-T supports up to 20 MHz SCK frequency when VCC is 4.5V to 5.5V, 10 MHz at 2.5V to 5.5V, and 5 MHz across the full 1.8V to 5.5V range. These limits are defined in the AC Characteristics table of the DS20006251A datasheet and reflect guaranteed timing margins for reliable read/write operation under specified voltage and temperature conditions. The AT25040B-MAHL-T must not be operated above these frequencies to ensure compliance with tSU, tH, and tV timing parameters.
Does the AT25040B-MAHL-T require external pull-up resistors on its SPI lines?
Yes - the AT25040B-MAHL-T requires a pull-up resistor (≤10 kΩ) on the CS pin to VCC for robust power-up behavior, as specified in Section 2.1 of the datasheet. While SO is internally tri-stated and SI/SCK/WP/HOLD are CMOS inputs with negligible leakage, system-level noise immunity and bus sharing may necessitate additional pull-ups on WP or HOLD depending on host controller drive strength and PCB layout. The AT25040B-MAHL-T itself does not integrate internal pull-ups on any pin.
How does write protection work on the AT25040B-MAHL-T?
The AT25040B-MAHL-T implements dual-layer write protection: hardware-based via the WP pin (low = all writes inhibited), and software-configurable via BP1/BP0 bits in the STATUS register (enabling 1/4, 1/2, or full array protection). WP takes precedence - if WP is low during CS assertion, no write command (including WRSR) will execute, regardless of STATUS register state. The AT25040B-MAHL-T retains BP bit settings across power cycles since they are stored in EEPROM.
Can the AT25040B-MAHL-T be used in SPI Mode 3 (CPOL=1, CPHA=1)?
Yes - the AT25040B-MAHL-T explicitly supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1), as confirmed in the Features section and Section 5.1 of the datasheet. In both modes, data is latched on the rising edge of SCK and output on the falling edge. The key requirement is that SCK idle state (high for Mode 3, low for Mode 0) must match before and after CS assertion. The AT25040B-MAHL-T does not support Modes 1 or 2.
What is the purpose of the HOLD pin on the AT25040B-MAHL-T?
The HOLD pin on the AT25040B-MAHL-T suspends ongoing SPI communication without resetting the internal command state or interrupting an active write cycle. When asserted (low) during SCK low time, it places SO in high-impedance and ignores SI/SCK inputs, allowing the host to pause transfers - e.g., to service higher-priority interrupts. Resuming requires deasserting HOLD during SCK low. The AT25040B-MAHL-T maintains full context (address pointer, opcode, partial byte) throughout hold, enabling seamless continuation.
AT25040B-MAHL-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT25040B-MAHL-T FAQ
1.How can I place an order for AT25040B-MAHL-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25040B-MAHL-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25040B-MAHL-T reliable?
The price and inventory of AT25040B-MAHL-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25040B-MAHL-T is usually 5 days.
3.What payment methods are accepted for AT25040B-MAHL-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25040B-MAHL-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25040B-MAHL-T?
AT25040B-MAHL-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25040B-MAHL-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25040B-MAHL-T?
For technical support, including AT25040B-MAHL-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25040B-MAHL-T requirements.
6.How does Aetrix verify that AT25040B-MAHL-T is sourced from the original manufacturer or authorized distributors?
All AT25040B-MAHL-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25040B-MAHL-T meets industry standards.
7.What is the process for return or replacement of AT25040B-MAHL-T?
All AT25040B-MAHL-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25040B-MAHL-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25040B-MAHL-T part is unused and in its original packaging.
Return procedure for AT25040B-MAHL-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25040B-MAHL-T Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
