My Inquiry
My Account
Microchip Technology AT25040B-XPD-T
- Part No.:
- AT25040B-XPD-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT25040B-XPD-T.pdf
- Description:
- IC EEPROM 4KBIT SPI 5MHZ 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,550
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25040B-XPD-T from Microchip Technology is a 4 Kbit (512 × 8) SPI-compatible automotive-grade serial EEPROM, supporting SPI Modes 0 and 3, operating from 1.7V to 5.5V, with AEC-Q100 Grade 3 qualification (–40°C to +85°C), 5 MHz max clock rate, and hardware/software write protection for use in engine control units and body electronics.
For engineers reviewing the AT25040B-XPD-T datasheet, AT25040B-XPD-T pinout, AT25040B-XPD-T application, or AT25040B-XPD-T equivalent, key selection criteria include its 8-byte page write capability, 1,000,000 write endurance, 100-year data retention, block-level write protection (1/4, 1/2, or full array), and dual-voltage operation across industrial and automotive supply rails.
Technical Context
The AT25040B-XPD-T implements a synchronous SPI slave interface with fixed MSb-first data framing, rising-edge input sampling on SI and falling-edge output latching on SO. Its internal architecture includes a nonvolatile STATUS register controlling BP1/BP0 block protection bits, WEL write-enable latch, and RDY/BSY status flag.
It supports hardware-based write inhibition via the WP pin and software-controlled protection via WRSR, with HOLD pin enabling pause/resume of ongoing SPI transfers without resetting the sequence. Internal self-timed write cycles complete within 5 ms maximum, independent of host timing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Kbit (512 × 8) EEPROM array - sufficient for firmware patch storage, calibration tables, or configuration registers in ECUs. |
| Supply voltage range | 1.7V to 5.5V - enables direct integration with 1.8V logic, 3.3V microcontrollers, and 5V legacy systems without level shifters. |
| Max clock frequency | 5 MHz at VCC = 5V - supports fast read/write bursts while maintaining timing margins per SPI Mode 0/3 specifications. |
| Write endurance | 1,000,000 cycles - ensures reliable logging and parameter updates over 10+ years of automotive service life. |
| Data retention | 100 years at 55°C - guarantees long-term integrity of safety-critical configuration data without refresh. |
| Operating temperature | –40°C to +85°C (AEC-Q100 Grade 3) - validated for under-hood and cabin-mounted automotive modules. |
| Page size | 8 bytes - minimizes bus occupancy during partial writes and reduces risk of corruption during power loss. |
Pinout & Package
AT25040B-XPD-T is supplied in an 8-lead SOIC package (XPD suffix), with gull-wing leads, 1.27 mm pitch, and JEDEC MS-012AC compliant outline. The package supports reflow soldering and meets RoHS, halide-free, and lead-free requirements.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be driven low before any instruction; requires pull-up resistor (≤10 kΩ) to VCC for robust power-up behavior. |
| SO | Serial Data Output | Tri-state output delivering MSb-first data on falling SCK edge; high-impedance when CS is high or HOLD is asserted. |
| WP | Write-Protect | Hardware lock: pulls low to inhibit all write operations including STATUS register changes; does not interrupt active internal writes. |
| GND | Ground reference | System ground connection for VCC return path and noise reference; must be low-impedance for stable SPI timing. |
| SI | Serial Data Input | MSb-first instruction/address/data input sampled on rising SCK edge; ignored during HOLD or when CS is high. |
| SCK | Serial Clock | Master-generated clock with idle polarity matching SPI Mode 0 (low) or Mode 3 (high); defines all timing windows per DS20006285B. |
| HOLD | Suspend Serial Input | Pauses SPI transfer mid-sequence when asserted low during SCK low; resumes on HOLD high during next SCK low; no effect on ongoing write cycle. |
| VCC | Power supply | 1.7V–5.5V input; requires monotonic ramp-up ≤0.1 V/µs and ≥100 µs delay after stability before first command. |
Key Features
| Feature | Design Value |
|---|---|
| Automotive qualification | AEC-Q100 Grade 3 certified - validated for automotive production use with full traceability and reliability testing. |
| Block write protection | Configurable via STATUS register (BP1/BP0) to protect 0%, 25%, 50%, or 100% of memory - prevents accidental overwrite of critical firmware sections. |
| Hardware + software write lock | WP pin provides immediate physical disable; WREN/WRDI instructions allow dynamic enable/disable under firmware control. |
| Hold function | Enables deterministic pause/resume of SPI transactions without clock stoppage or command restart - essential for real-time system arbitration. |
| Green packaging | RoHS-compliant, halide-free, lead-free SOIC - meets global environmental compliance requirements for automotive OEMs. |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
|
Use Scenario: Storing adaptive fuel trim values, misfire counters, and diagnostic trouble codes (DTCs) that persist across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile configuration and event logging storage interfaced directly to MCU SPI peripheral with minimal GPIO overhead. Use Value: 1,000,000 write cycles and 100-year retention ensure DTC history remains intact over vehicle lifetime without battery backup. |
Use Scenario: Holding camera calibration offsets, radar sensor fusion parameters, and lane-departure warning thresholds updated during factory calibration or OTA updates. IC Role / Device Role / Timing Role: Secure, protected storage for safety-critical configuration data accessed via SPI during boot and runtime. Use Value: Block write protection prevents unintended modification of calibrated values during field operation or firmware updates. |
| Body Control Module (BCM) | Infotainment System Settings |
|
Use Scenario: Retaining user preferences (window position, mirror angle, seat memory) and door-lock programming across power cycles. IC Role / Device Role / Timing Role: Low-power serial EEPROM accessed intermittently by BCM microcontroller using standard SPI protocol. Use Value: 1.7V operation allows direct connection to 1.8V logic domains; 8-byte page writes minimize bus contention during multi-parameter saves. |
Use Scenario: Saving audio equalizer presets, display brightness profiles, and Bluetooth pairing information between sessions. IC Role / Device Role / Timing Role: Persistent storage element co-located with infotainment SoC, leveraging existing SPI bus infrastructure. Use Value: Hardware WP pin enables permanent locking of factory-default settings while allowing user-modifiable regions to remain writable. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95040-DRMN6TP/K | 4 Kbit SPI EEPROM, 2.5V–5.5V, 20 MHz max clock, SO8 package, but not AEC-Q100 qualified. | Lacks automotive qualification; suitable for industrial or consumer designs where extended temperature and reliability validation are not required. | Select when higher speed (20 MHz) is needed and automotive qualification is unnecessary. |
| BR24G04FJ-3GE2 | 4 Kbit I²C EEPROM, 1.7V–5.5V, 1 MHz max clock, TSSOP8, AEC-Q100 Grade 2 (–40°C to +105°C). | Uses I²C instead of SPI; slower interface; different pinout and command set; requires two GPIOs (SCL/SDA) vs. four for SPI. | Select when board already uses I²C bus and space constraints favor TSSOP8; verify timing compatibility with host controller. |
Compared with M95040-DRMN6TP/K and BR24G04FJ-3GE2, the AT25040B-XPD-T uniquely combines AEC-Q100 Grade 3 qualification, SPI interface compatibility, 5 MHz performance, and 1.7V operation in a standard SOIC package-making it optimal for cost-sensitive, SPI-based automotive modules requiring guaranteed reliability.
Availability
AT25040B-XPD-T is available at Aetrix Electronics and suitable for engine control units, ADAS sensors, and body control modules requiring stable component supply, long-lifecycle support, and automotive-grade traceability.
Supply support for AT25040B-XPD-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and memory products, with broad automotive, industrial, and communications market presence.
The AT25040B-XPD-T belongs to Microchip's automotive-qualified serial EEPROM product line, designed specifically for reliable nonvolatile data storage in harsh-temperature, safety-critical electronic control systems.
FAQ
What is the operating voltage range for the AT25040B-XPD-T?
The AT25040B-XPD-T operates from 1.7V to 5.5V, supporting both low-voltage (1.8V logic) and standard 5V systems. This dual-range capability eliminates the need for external level shifters in mixed-voltage designs and ensures compatibility with modern automotive MCUs. The device maintains full functionality-including 5 MHz clock rate and write protection-across the entire voltage range.
Does the AT25040B-XPD-T support SPI Mode 3, and how is it configured?
Yes, the AT25040B-XPD-T supports both SPI Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 0). No configuration is required-the device automatically adapts based on SCK idle state: high for Mode 3, low for Mode 0. The SCK polarity must remain consistent before and after CS assertion to avoid communication errors. Timing parameters in DS20006285B apply to both modes.
How does the HOLD pin function during an active write cycle in the AT25040B-XPD-T?
The HOLD pin has no effect on an ongoing internal write cycle in the AT25040B-XPD-T. While HOLD can pause SPI command transmission (e.g., mid-read or mid-address phase), it does not suspend or abort the self-timed 5 ms write operation once initiated. The device continues writing to EEPROM cells regardless of HOLD state. Only WP or power loss can interrupt a write, and WP must be asserted before the internal cycle starts to take effect.
What protection mechanisms prevent unintended writes to the AT25040B-XPD-T memory array?
The AT25040B-XPD-T employs three layered protections: (1) hardware write disable via the WP pin (low = all writes blocked), (2) software-controlled Write Enable Latch (WEL bit set only after WREN command), and (3) nonvolatile Block Protection bits (BP1/BP0) that lock 25%, 50%, or 100% of the array. All three operate independently-WP overrides WEL, and BP bits restrict address ranges even when WEL is set.
Is the AT25040B-XPD-T pin-compatible with other members of the AT250xxB family?
Yes, the AT25040B-XPD-T shares identical pinout, package (8-lead SOIC), and SPI interface behavior with AT25010B-XPD-T and AT25020B-XPD-T. Differences are limited to memory density (1K/2K/4K) and internal addressing-no PCB redesign is needed when scaling capacity. All share the same STATUS register layout, opcodes, timing specs, and AEC-Q100 Grade 3 qualification.
AT25040B-XPD-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 5 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT25040B-XPD-T FAQ
1.How can I place an order for AT25040B-XPD-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25040B-XPD-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25040B-XPD-T reliable?
The price and inventory of AT25040B-XPD-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25040B-XPD-T is usually 5 days.
3.What payment methods are accepted for AT25040B-XPD-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25040B-XPD-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25040B-XPD-T?
AT25040B-XPD-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25040B-XPD-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25040B-XPD-T?
For technical support, including AT25040B-XPD-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25040B-XPD-T requirements.
6.How does Aetrix verify that AT25040B-XPD-T is sourced from the original manufacturer or authorized distributors?
All AT25040B-XPD-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25040B-XPD-T meets industry standards.
7.What is the process for return or replacement of AT25040B-XPD-T?
All AT25040B-XPD-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25040B-XPD-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25040B-XPD-T part is unused and in its original packaging.
Return procedure for AT25040B-XPD-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25040B-XPD-T Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
