Microchip Technology AT25040N-10SI
- Part No.:
- AT25040N-10SI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25040N-10SI.pdf
- Description:
- IC EEPROM 4KBIT SPI 3MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,811
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25040N-10SI from Atmel (now Microchip) is a 4-kbit SPI serial EEPROM organized as 512 × 8-bit memory, operating from 2.7V to 5.5V with industrial temperature range (−40°C to +85°C), 2.1 MHz max clock rate at 5V, and 8-byte page write capability. It serves as nonvolatile configuration storage in microcontroller-based systems requiring reliable, low-power data retention.
For engineers reviewing the AT25040N-10SI datasheet, AT25040N-10SI pinout, AT25040N-10SI application, or AT25040N-10SI equivalent, key selection criteria include its industrial-grade SOIC-8 package, hardware/software write protection via WP pin and status register, self-timed 10 ms write cycle, 1 million endurance cycles, and SPI Mode 0/3 compatibility with 68HC11/6805 microcontrollers.
Technical Context
The AT25040N-10SI implements a synchronous SPI slave interface with dedicated SI (input), SO (output), SCK (clock), CS (chip select), WP (write protect), and HOLD (communication suspend) pins. Its instruction set includes WREN/WRDI for write enable/disable control and RDSR/WRSR for status register access and block-level write protection (1/4, 1/2, or full array).
It supports three voltage ranges-1.8V, 2.7V, and 5.0V-with this specific variant rated for 2.7V–5.5V operation and industrial temperature grade. All programming is self-timed with no external erase cycle required, and the device powers up in write-disabled state, requiring explicit WREN before any WRITE command.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4 kbit (512 words × 8 bits), sufficient for firmware calibration tables or device configuration registers |
| Interface | SPI-compatible slave with Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1) support |
| Supply Voltage | 2.7V to 5.5V - enables direct integration with 3.3V and 5V logic systems without level shifting |
| Max Clock Frequency | 2.1 MHz at VCC = 5V - allows fast read/write transfers in time-critical embedded boot sequences |
| Write Cycle Time | 10 ms maximum - defines minimum interval between successive page writes; no polling needed beyond RDSR status check |
| Endurance & Retention | 1 million write cycles and 100-year data retention - suitable for long-life industrial field devices with infrequent updates |
| Operating Temperature | −40°C to +85°C - qualified for industrial environments including motor controls and sensor nodes |
Pinout & Package
AT25040N-10SI is supplied in an 8-pin JEDEC SOIC (8S1) package, 0.150" wide, with gull-wing leads and standard footprint compatible with automated PCB assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be low to accept commands; high impedance on SO when CS is high |
| SCK | Serial Clock | Input-only master-generated clock; timing critical for setup/hold compliance per AC specs |
| SI | Serial Data Input | Receives op-codes, addresses, and data; MSB-first transmission required |
| SO | Serial Data Output | Tri-state output delivering read data or status bits; high-Z when CS high or during HOLD |
| WP | Write Protect | Hardware lock: low disables all write operations regardless of status register or WREN state |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer without resetting sequence; requires SCK low during assertion |
| VCC | Power Supply | 2.7V–5.5V input; decoupling capacitor recommended near pin for noise immunity |
| GND | Ground | Reference return path for all digital and power signals; shared with system ground plane |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Configurable via status register to protect 1/4, 1/2, or entire memory array - prevents accidental overwrites of critical calibration or security data |
| Dual Write Protection | Combines hardware (WP pin) and software (WREN + status register) methods - ensures robustness against both electrical faults and firmware bugs |
| Page Write Mode | 8-byte burst write within same page - reduces transaction overhead vs. byte-by-byte writes, improving update efficiency in parameter storage |
| HOLD Functionality | Non-disruptive pause of SPI communication - allows host MCU to service higher-priority interrupts without losing EEPROM transaction context |
| Industrial Temperature Grade | −40°C to +85°C operation - validated for deployment in automotive body controllers, industrial PLC I/O modules, and outdoor metering equipment |
Applications
| Smart Sensor Calibration Storage | Industrial PLC Configuration Memory |
|---|---|
|
Use Scenario: Storing factory-calibrated offset/gain coefficients and linearization tables for analog sensor front-ends in environmental monitoring nodes. IC Role / Device Role / Timing Role: Nonvolatile configuration store accessed during power-up initialization; read-only during normal operation. Use Value: Enables plug-and-play sensor replacement with pre-loaded calibration data, eliminating field recalibration and reducing maintenance downtime. |
Use Scenario: Holding user-defined I/O mapping, alarm thresholds, and communication protocol settings in modular programmable logic controllers. IC Role / Device Role / Timing Role: Persistent parameter repository updated only during commissioning or firmware upgrade; accessed via SPI during boot and runtime queries. Use Value: Supports flexible reconfiguration without firmware changes, allowing end-users to adapt logic behavior without engineering intervention. |
| Medical Device Setup Parameters | Automotive Body Control Module Settings |
|
Use Scenario: Retaining operator-selected modes (e.g., alarm sensitivity, display brightness, language) in portable diagnostic instruments. IC Role / Device Role / Timing Role: Low-power EEPROM interfaced to ARM Cortex-M0+ MCU; written infrequently but read at every power-on reset. Use Value: Maintains user preferences across battery replacements and power cycles, meeting IEC 62304 Class B data integrity requirements. |
Use Scenario: Storing vehicle-specific configuration such as door lock behavior, mirror fold settings, and lighting profiles in BCMs. IC Role / Device Role / Timing Role: SPI-connected nonvolatile memory updated via CAN gateway during dealership programming or OTA updates. Use Value: Enables VIN-locked personalization features while supporting secure write-protection to prevent unauthorized tampering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95040-DRMN6TP/K | 4-kbit SPI EEPROM, 1.8V–5.5V, SOIC-8, 20 MHz max clock, 5 ms write cycle | Higher speed and lower write latency; lacks HOLD pin; different status register layout | Preferred where faster parameter updates are needed and HOLD functionality is unused |
| BR24G04FJ-WE2 | 4-kbit I²C EEPROM, 1.7V–5.5V, TSSOP-8, 1 MHz max clock, 5 ms write cycle | I²C interface instead of SPI; no WP/HOLD pins; uses ACK polling instead of RDSR for busy detection | Selected when board already uses I²C bus and SPI lines are constrained |
Compared with M95040-DRMN6TP/K and BR24G04FJ-WE2, the AT25040N-10SI offers deterministic HOLD-based transaction suspension and dual-mode SPI compatibility, making it optimal for legacy 68HC11/6805 designs and industrial systems requiring guaranteed interrupt-safe EEPROM access.
Availability
AT25040N-10SI is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, and medical instrumentation requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for AT25040N-10SI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation, now part of Microchip Technology, is a semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for embedded systems.
The AT250xx family was designed specifically for SPI-based configuration and parameter storage in resource-constrained microcontroller applications, emphasizing low-voltage operation, industrial reliability, and pin-efficient serial interfacing.
FAQ
What is the maximum clock frequency supported by the AT25040N-10SI at 3.3V operation?
The AT25040N-10SI supports up to 2.1 MHz at VCC = 5.0V, and 2.1 MHz at VCC = 2.7V–5.5V per AC Characteristics table. At 3.3V, it operates at the full 2.1 MHz rating - confirmed in the "Voltage" column for fSCK under 2.7–5.5V conditions. This allows high-throughput reads during system boot without requiring clock throttling.
Does the AT25040N-10SI require an external erase command before writing new data?
No, the AT25040N-10SI does not require a separate erase command. Each WRITE instruction automatically erases and programs the target byte(s) in a single self-timed operation. The internal write cycle completes within 10 ms maximum, and the device returns to standby mode upon completion - verified in the Functional Description and AC Characteristics sections.
How does the HOLD pin function during an active SPI read sequence on the AT25040N-10SI?
During an active SPI read, asserting HOLD low (while SCK is low) suspends data output on SO and halts address incrementing without resetting the transaction. When HOLD is returned high (with SCK still low), the AT25040N-10SI resumes exactly where it left off - delivering the next byte from the incremented address. This behavior is explicitly defined in the HOLD section of the Serial Interface Description.
Can the AT25040N-10SI be used in a 1.8V system?
No - the AT25040N-10SI is specified for 2.7V to 5.5V operation only. While the broader AT25040 family includes -1.8 variants (e.g., AT25040N-10SI-1.8), this exact part number carries the "-2.7" option suffix in its ordering row (AT25040N-10SI-2.7), confirming its 2.7V minimum VCC. Using it below 2.7V risks data corruption or functional failure.
What happens if the WP pin is pulled low during a WRITE instruction on the AT25040N-10SI?
If WP is driven low while CS is active and a WRITE instruction is in progress, the AT25040N-10SI immediately inhibits the write operation - even if the internal write cycle has started. The device ignores subsequent data and reverts to standby mode when CS goes high. This hardware lock overrides all software protections and is documented in the WRITE PROTECT section of the datasheet.
AT25040N-10SI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 3 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25040N-10SI FAQ
1.How can I place an order for AT25040N-10SI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25040N-10SI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25040N-10SI reliable?
The price and inventory of AT25040N-10SI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25040N-10SI is usually 5 days.
3.What payment methods are accepted for AT25040N-10SI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25040N-10SI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25040N-10SI?
AT25040N-10SI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25040N-10SI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25040N-10SI?
For technical support, including AT25040N-10SI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25040N-10SI requirements.
6.How does Aetrix verify that AT25040N-10SI is sourced from the original manufacturer or authorized distributors?
All AT25040N-10SI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25040N-10SI meets industry standards.
7.What is the process for return or replacement of AT25040N-10SI?
All AT25040N-10SI units undergo pre-shipment inspection (PSI). If there is an issue with AT25040N-10SI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25040N-10SI part is unused and in its original packaging.
Return procedure for AT25040N-10SI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25040N-10SI Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
