Microchip Technology AT25080A-10TU-1.8-T
- Part No.:
- AT25080A-10TU-1.8-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT25080A-10TU-1.8-T.pdf
- Description:
- IC EEPROM 8KBIT SPI 20MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,076
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25080A-10TU-1.8-T from Microchip Technology (formerly Atmel) is an 8-Kbit SPI serial EEPROM organized as 1024 × 8 bits, operating from 1.8 V to 5.5 V, supporting 20 MHz clock rate at 5 V, featuring 32-byte page write mode and hardware/software write protection via WP pin and status register. It is used in industrial control systems for firmware parameter storage requiring low-voltage operation and long-term data retention.
For engineers reviewing the AT25080A-10TU-1.8-T datasheet, AT25080A-10TU-1.8-T pinout, AT25080A-10TU-1.8-T application, or AT25080A-10TU-1.8-T equivalent, this page delivers verified electrical specs, TSSOP-8 package details, SPI Mode 0/3 compatibility, block write protection configuration, and real-world use cases in embedded systems with constrained power budgets.
Technical Context
The AT25080A-10TU-1.8-T implements a synchronous SPI slave interface with separate SI/SO lines, MSB-first data transfer, and CS-driven selection. It uses an 8-bit instruction register with op-codes for WREN, WRDI, RDSR, WRSR, READ, and WRITE - all requiring CS falling edge initiation.
Its internal architecture supports automatic address increment during page writes, READY/BUSY flag reporting via RDSR (Bit 0), and nonvolatile BP0/BP1/WPEN bits enabling 0%, 25%, 50%, or 100% array protection. The HOLD pin suspends ongoing transfers without resetting sequence state, while WP pin blocks status register writes when WPEN = 1 and WP = low.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 8 Kbit (1024 words × 8 bits); sufficient for bootloader config, calibration tables, or device identity storage in space-constrained designs. |
| Supply Voltage Range | 1.8 V to 5.5 V; enables direct interfacing with 1.8 V logic families and backward compatibility with 3.3 V/5 V microcontrollers. |
| Max Clock Frequency | 20 MHz at VCC = 5 V; supports high-throughput parameter updates in real-time control loops. |
| Page Write Size | 32 bytes; minimizes write latency versus byte-write EEPROMs and reduces host MCU overhead during bulk configuration writes. |
| Write Endurance | 1 million cycles; ensures reliable field reprogramming over product lifetime in telemetry or logging applications. |
| Data Retention | 100 years at +25 °C; guarantees persistent storage of critical settings without battery backup. |
| Operating Temperature | –40 °C to +85 °C; qualified for industrial environments including motor drives and sensor nodes. |
Pinout & Package
AT25080A-10TU-1.8-T is packaged in an 8-lead TSSOP (8A2) with 4.4 mm body width, RoHS-compliant lead finish, and 0.65 mm pitch - optimized for automated PCB assembly and thermal performance in dense layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be driven low before SPI transaction begins and held stable during SCK activity. |
| SCK | Serial Clock | Input-only clock line; synchronizes all SI/SO data transfers; supports Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). |
| SI | Serial Data Input | Master-to-slave data path; accepts op-codes, addresses, and write data on rising edge of SCK in Mode 0. |
| SO | Serial Data Output | Slave-to-master data path; outputs read data and status register contents on falling edge of SCK in Mode 0. |
| GND | Ground Reference | Primary return path for VCC and I/O signals; requires low-impedance connection to system ground plane. |
| VCC | Power Supply | Single supply input; supports 1.8–5.5 V operation; bypass capacitor (0.1 µF) recommended near pin. |
| WP | Write Protect | Hardware lock for status register; disables writes to BP0/BP1/WPEN when WP = low and WPEN = 1. |
| HOLD | Communication Suspend | Pauses active SPI transfer without resetting internal address counter; resumes on rising edge while SCK is low. |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Configurable 0%/25%/50%/100% memory locking via nonvolatile BP0/BP1 bits - prevents accidental overwrite of boot code or calibration data. |
| Self-timed Write Cycle | Max 5 ms internal erase/write; eliminates need for external timing control or polling delay beyond RDSR readiness check. |
| Dual Write Enable | Combines software WREN instruction with hardware WP pin - provides layered security against unintended writes during power-up or noise events. |
| Low-Voltage Operation | Guaranteed functionality down to 1.8 V - enables direct integration with ultra-low-power MCUs like ARM Cortex-M0+ without level-shifting. |
| HOLD Functionality | Preserves serial sequence state during interrupt servicing - avoids reinitialization overhead when host MCU handles time-critical tasks. |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
Use Scenario: Storing factory-calibrated gain/offset coefficients and temperature compensation curves for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile parameter repository accessed during power-on initialization and runtime recalibration routines. Use Value: Enables field-upgradable calibration without firmware reflashing; 100-year retention ensures accuracy across equipment lifecycle. | Use Scenario: Holding user-selectable therapy parameters (e.g., infusion rate limits, alarm thresholds) in portable insulin pumps and dialysis monitors. IC Role / Device Role / Timing Role: Secure, low-power configuration store accessed via SPI during GUI navigation and safety-critical setup sequences. Use Value: WP pin + BP bits prevent unauthorized modification of life-safety settings; 1.8 V operation extends battery life between charges. |
| Automotive Body Control Module | Smart Energy Metering |
Use Scenario: Recording door lock/unlock history, mirror position presets, and lighting profiles in vehicle BCMs compliant with AEC-Q100 Grade 3. IC Role / Device Role / Timing Role: SPI-configurable memory node on LIN or CAN gateway subsystems, updated during dealer diagnostics. Use Value: –40 °C to +85 °C rating ensures reliability under hood temperature cycling; 1M endurance supports daily usage over 10+ years. | Use Scenario: Storing tariff schedules, billing cycle counters, and tamper-detection logs in DIN-rail mounted electricity meters deployed globally. IC Role / Device Role / Timing Role: Secure data logger interfaced to metrology SoC via isolated SPI bus, retaining data through mains brownouts. Use Value: Block protection isolates tariff tables from firmware update routines; 5 ms write time enables fast log commits during grid transients. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95080-DRMN6TP/K | STMicroelectronics 8-Kbit SPI EEPROM; identical 1.8–5.5 V range and 20 MHz max clock, but uses different status register bit mapping for BP bits and lacks HOLD pin. | Requires firmware adaptation for BP configuration and no suspend capability during SPI transfers. | Select if HOLD functionality is unused and ST's qualification support (e.g., automotive AEC-Q100) is preferred. |
| BR24G08NUX-10 | Rohm 8-Kbit SPI EEPROM; supports 1.6–5.5 V, includes built-in write protect latch, but only offers 10 MHz max speed at 1.8 V and no hardware WP pin. | Limited bandwidth for high-speed parameter updates; relies solely on software WREN/WRDI for protection. | Choose for ultra-low-voltage systems (<1.8 V) where 10 MHz suffices and board space allows larger SOIC-8 footprint. |
Compared with M95080-DRMN6TP/K and BR24G08NUX-10, the AT25080A-10TU-1.8-T uniquely combines HOLD pin support, standardized BP bit layout per JEDEC, and guaranteed 20 MHz operation across full 1.8–5.5 V range - making it optimal for industrial designs requiring deterministic SPI pause/resume and robust dual-layer write security.
Availability
AT25080A-10TU-1.8-T is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, automotive body control modules, and smart energy metering requiring stable component supply and long-term obsolescence management.
Supply support for AT25080A-10TU-1.8-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with broad industrial and automotive qualifications.
The AT25080A-10TU-1.8-T belongs to Microchip's legacy serial EEPROM product line, designed specifically for reliable, low-power nonvolatile storage in resource-constrained embedded systems interfacing directly with SPI-capable microcontrollers.
FAQ
What is the maximum clock frequency supported by the AT25080A-10TU-1.8-T at 1.8 V?
The AT25080A-10TU-1.8-T supports up to 5 MHz at 1.8 V, as specified in Table 1-3 AC Characteristics. This is lower than its 20 MHz maximum at 5 V but ensures robust timing margins and signal integrity in ultra-low-voltage applications such as battery-powered IoT sensors.
Does the AT25080A-10TU-1.8-T require an external pull-up resistor on the SO pin?
No, the AT25080A-10TU-1.8-T features an internally controlled tri-state output driver on the SO pin. When CS is high or during HOLD assertion, SO enters high-impedance state without needing external pull-ups - simplifying PCB design and reducing BOM count.
How does the WP pin interact with the WPEN bit in the status register of the AT25080A-10TU-1.8-T?
When WPEN = 1, the WP pin actively blocks writes to the status register (including BP0/BP1 bits) if pulled low. If WPEN = 0, the WP pin is ignored entirely, allowing full status register access regardless of WP voltage - enabling flexible system-level protection schemes during manufacturing or field service.
Can the AT25080A-10TU-1.8-T be used in SPI Mode 3 (CPOL=1, CPHA=1)?
Yes, the AT25080A-10TU-1.8-T explicitly supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1), as stated in its Features section. Designers must configure the host controller accordingly - Mode 3 is often selected to match legacy microcontroller peripherals with inverted clock polarity requirements.
What is the write cycle time for a single byte versus a full 32-byte page on the AT25080A-10TU-1.8-T?
Both single-byte and 32-byte page writes complete within a maximum of 5 ms, as the AT25080A-10TU-1.8-T performs self-timed internal erase-and-program operations. Page writes improve host efficiency by reducing command overhead, but do not reduce total programming latency per byte - the 5 ms bound applies to any write operation.
AT25080A-10TU-1.8-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 8Kbit
- Memory Organization:
- 1K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT25080A-10TU-1.8-T FAQ
1.How can I place an order for AT25080A-10TU-1.8-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25080A-10TU-1.8-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25080A-10TU-1.8-T reliable?
The price and inventory of AT25080A-10TU-1.8-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25080A-10TU-1.8-T is usually 5 days.
3.What payment methods are accepted for AT25080A-10TU-1.8-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25080A-10TU-1.8-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25080A-10TU-1.8-T?
AT25080A-10TU-1.8-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25080A-10TU-1.8-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25080A-10TU-1.8-T?
For technical support, including AT25080A-10TU-1.8-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25080A-10TU-1.8-T requirements.
6.How does Aetrix verify that AT25080A-10TU-1.8-T is sourced from the original manufacturer or authorized distributors?
All AT25080A-10TU-1.8-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25080A-10TU-1.8-T meets industry standards.
7.What is the process for return or replacement of AT25080A-10TU-1.8-T?
All AT25080A-10TU-1.8-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25080A-10TU-1.8-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25080A-10TU-1.8-T part is unused and in its original packaging.
Return procedure for AT25080A-10TU-1.8-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25080A-10TU-1.8-T Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
