Microchip Technology AT25080B-MAHL-T
- Part No.:
- AT25080B-MAHL-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT25080B-MAHL-T.pdf
- Description:
- IC EEPROM 8KBIT SPI 20MHZ 8UDFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT25080B-MAHL-T from Microchip Technology is an 8 Kbit SPI Serial EEPROM (1,024 × 8) in an 8-lead SOIC package, supporting SPI Modes 0 and 3, operating from 1.8V to 5.5V, with 20 MHz max clock rate at 5V, 32-byte page write capability, and industrial temperature range (−40°C to +85°C). It serves as nonvolatile configuration storage in microcontroller-based embedded systems requiring reliable, low-voltage data retention.
For engineers reviewing the AT25080B-MAHL-T datasheet, AT25080B-MAHL-T pinout, AT25080B-MAHL-T application, or AT25080B-MAHL-T equivalent, key selection considerations include its 1.8V–5.5V supply range, hardware/software write protection via WP pin and STATUS register, 5 ms max self-timed write cycle, 1M endurance, and 100-year data retention - critical for firmware parameter storage, calibration data logging, and secure boot configuration in space-constrained industrial designs.
Technical Context
The AT25080B-MAHL-T implements a synchronous SPI slave interface with fixed 8-bit opcode decoding, MSb-first data transfer, and dual-mode SCK polarity support (Mode 0 idle-low, Mode 3 idle-high). Its internal architecture includes a high-voltage generation circuit for EEPROM programming, address register and counter, row/column decoders, and a dedicated STATUS register bank controlling write enable, block protection (BP1/BP0), and write-protect enable (WPEN).
It features dual-level write protection: hardware-based via the WP pin (active-low, conditional on WPEN bit), and software-configurable block protection covering 1/4, 1/2, or full memory array. The HOLD pin enables real-time suspension of ongoing serial transfers without resetting the command sequence - preserving state during host interrupt servicing while maintaining SO high-impedance and ignoring SI/SCK inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 8 Kbits (1,024 × 8) - provides sufficient nonvolatile storage for device configuration, calibration coefficients, or small firmware metadata without requiring larger, costlier EEPROMs. |
| Supply voltage | 1.8V to 5.5V - enables direct interfacing with 1.8V, 3.3V, and 5V microcontrollers without level-shifting, simplifying power domain integration. |
| Max clock frequency | 20 MHz at 5V - supports fast read/write throughput (up to ~2.5 MB/s theoretical SPI bandwidth) for time-critical parameter updates. |
| Page size | 32 bytes - limits maximum atomic write burst; requires host firmware to manage multi-page writes across 1,024-word address space. |
| Write endurance | 1,000,000 cycles - ensures long-term reliability in applications with frequent reconfiguration (e.g., energy meter tariff tables, sensor offset adjustments). |
| Data retention | 100 years at 55°C - guarantees persistent storage integrity over product lifetime, even under elevated thermal stress in industrial enclosures. |
| Operating temperature | −40°C to +85°C - qualified for deployment in uncontrolled environments including factory automation, outdoor gateways, and automotive body control modules. |
| Write cycle time | ≤5 ms (self-timed) - eliminates need for external polling delay; host can issue next command after tWC timeout without status polling overhead. |
Pinout & Package
AT25080B-MAHL-T is packaged in an 8-lead SOIC (Small Outline Integrated Circuit) with standard JEDEC MS-012AC footprint (5.3 mm × 4.4 mm, 1.27 mm pitch). Pin functions are electrically identical across all AT25080B package variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be driven low before any SPI transaction; requires pull-up resistor (≤10 kΩ) tied to VCC for robust power-up behavior. |
| SO | Serial Data Output | Tri-state output delivering MSb-first data on falling edge of SCK; enters high-impedance when CS is high or HOLD is asserted. |
| WP | Write-Protect | Hardware lock for STATUS register writes when WPEN=1; tied high for normal operation; grounded only when permanent protection of BP bits is required. |
| GND | Ground Reference | System ground return path for VCC and all I/O signals; must be low-impedance connection to minimize noise coupling into EEPROM core. |
| SI | Serial Data Input | MSb-first input for opcodes, addresses, and write data; sampled on rising edge of SCK; ignored during HOLD or when CS is high. |
| SCK | Serial Clock | Master-generated clock synchronizing all SPI transfers; supports Mode 0 (idle low) and Mode 3 (idle high); timing constraints scale with VCC. |
| HOLD | Suspend Control | Pauses ongoing SPI communication without resetting state; asserted low during SCK low phase; preserves internal address pointer and command context. |
| VCC | Power Supply | Primary power rail (1.8V–5.5V); requires local 100 nF ceramic decoupling capacitor placed within 5 mm of VCC/GND pins. |
Key Features
| Feature | Design Value |
|---|---|
| Triple-voltage compatibility | Operates across 1.8V, 3.3V, and 5V logic domains - eliminates need for external level shifters in mixed-supply systems. |
| Hardware + software write protection | Combines WP pin (physical lock) and STATUS register BP1/BP0 bits (configurable 25%/50%/100% array lock) for layered security against accidental overwrite. |
| Hold function with state preservation | Interrupts SPI transfers mid-sequence without losing address pointer or command context - essential for deterministic real-time host interrupt handling. |
| Green RoHS-compliant packaging | Lead-free, halide-free SOIC package meets IPC/JEDEC J-STD-020 moisture sensitivity level 3 (MSL3), enabling standard reflow assembly. |
| Fast 5 ms write cycle | Self-timed internal programming eliminates host polling overhead; allows predictable worst-case latency for configuration updates. |
| 100-year data retention | Validated at 55°C - exceeds typical industrial product lifetimes, reducing risk of field failures due to data corruption in long-deployment equipment. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Logging |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory environments with wide ambient temperature swings. IC Role / Device Role / Timing Role: Nonvolatile configuration register holding user-defined operational settings; accessed infrequently but must survive power loss and retain integrity over 15+ years. Use Value: AT25080B-MAHL-T's −40°C to +85°C rating, 100-year retention, and 1M write cycles ensure configuration persistence across PLC service life without battery backup or refresh routines. |
Use Scenario: Recording sensor calibration offsets, manufacturing test results, and regulatory compliance timestamps in portable diagnostic instruments subject to periodic recalibration. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter vault; write-protected via WP pin during normal operation to prevent accidental erasure of certified calibration values. Use Value: Hardware WP + STATUS register BP bits provide dual-layer protection; 1.8V operation enables direct interface with low-power medical SoCs, minimizing system BOM count. |
| Smart Energy Meter Firmware Metadata | Automotive Body Control Module Settings |
Use Scenario: Storing tariff schedules, firmware version fingerprints, and cryptographic keys in utility-grade electricity meters exposed to outdoor thermal cycling and EMI. IC Role / Device Role / Timing Role: Trusted configuration anchor for secure boot chain; accessed during startup and firmware update; must withstand >10,000 write cycles over 20-year field life. Use Value: AT25080B-MAHL-T's 1M endurance, 5 ms write time, and RoHS-compliant SOIC package meet ANSI C12.22 and IEC 62056 requirements for metrology-grade nonvolatile storage. |
Use Scenario: Retaining seat position presets, mirror angle configurations, and lighting profiles in automotive BCMs where EEPROM must operate reliably across −40°C cold cranking and +85°C under-hood conditions. IC Role / Device Role / Timing Role: Persistent user preference store; written during vehicle power-down sequence; read at ignition-on; requires guaranteed data integrity after 15+ years. Use Value: AT25080B-MAHL-T's industrial temp grade, 100-year retention, and 1.8V–5.5V supply range eliminate need for external voltage translators or thermal derating margins in BCM designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95080-DFMN6TP | 8 Kbit SPI EEPROM (1,024 × 8), 20 MHz @ 5V, same SOIC-8 package, but uses different STATUS register layout and lacks HOLD pin functionality. | Supports basic read/write and WP-based protection only; no suspend capability - unsuitable for hosts requiring interrupt-safe SPI pauses. | Select M95080-DFMN6TP only if HOLD functionality is unused and STMicroelectronics supply chain alignment is prioritized. |
| BR24G08NUX-10 | 8 Kbit I²C EEPROM (1,024 × 8), 1 MHz max clock, 1.7V–5.5V supply, same SOIC-8 footprint, but uses two-wire interface instead of SPI. | Requires I²C-capable MCU peripherals; slower than AT25080B-MAHL-T's 20 MHz SPI; no hardware HOLD or WP pin - relies solely on software lock bits. | Choose BR24G08NUX-10 only when board layout already uses I²C buses and SPI resources are constrained; not drop-in compatible. |
Compared with M95080-DFMN6TP and BR24G08NUX-10, the AT25080B-MAHL-T uniquely delivers SPI Mode 0/3 interoperability, hardware HOLD for deterministic interrupt handling, and dual-mode write protection - making it the optimal choice for real-time embedded systems where timing predictability and robust data integrity are non-negotiable.
Availability
AT25080B-MAHL-T is available at Aetrix Electronics and suitable for industrial PLC configuration storage, medical device calibration logging, and smart energy meter firmware metadata requiring stable component supply, long-lifecycle assurance, and RoHS-compliant manufacturing readiness.
Supply support for AT25080B-MAHL-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The AT25080B-MAHL-T belongs to Microchip's AT25xxx family of SPI Serial EEPROMs, engineered specifically for low-power, wide-voltage-range nonvolatile storage in resource-constrained embedded systems demanding high reliability and long-term data integrity.
FAQ
What is the maximum clock frequency supported by AT25080B-MAHL-T at 3.3V operation?
The AT25080B-MAHL-T supports up to 10 MHz SCK frequency when VCC = 2.5V to 5.5V, per Table 4-3 of the datasheet. At 3.3V, this applies directly - enabling reliable high-speed reads and writes without timing violations. This is lower than its 20 MHz rating at 5V but still sufficient for most microcontroller-based applications requiring sub-100 µs parameter access.
Does AT25080B-MAHL-T require external pull-up resistors on its SPI lines?
Yes, AT25080B-MAHL-T requires a pull-up resistor (≤10 kΩ) on the CS pin to VCC for robust power-up behavior, as specified in Section 2.1 of the datasheet. SO is internally tri-stated and does not require pull-up; SI, SCK, WP, and HOLD are CMOS inputs and may need pull-ups depending on host driver strength and PCB routing - though not mandated by the device itself.
How does the HOLD pin function during an active write cycle in AT25080B-MAHL-T?
The HOLD pin has no effect on an ongoing internal write cycle in AT25080B-MAHL-T. As stated in Section 5.3, Hold mode suspends serial communication only - it does not pause or abort the self-timed 5 ms EEPROM programming operation. The write completes autonomously, and the device remains busy until tWC expires, regardless of HOLD state.
Can AT25080B-MAHL-T be used with SPI Mode 1 or Mode 2 interfaces?
No, AT25080B-MAHL-T explicitly supports only SPI Modes 0 and 3, as confirmed in the Features section and Section 5. The device latches data on the rising edge and outputs on the falling edge of SCK - incompatible with Mode 1 (sample on falling, output on rising) and Mode 2 (idle high, sample on falling). Using unsupported modes will result in corrupted reads/writes.
What is the default state of the STATUS register after power-up in AT25080B-MAHL-T?
At power-up, the AT25080B-MAHL-T defaults to Standby mode with WEL = 0 (write disabled), Ready/Busy = 0 (ready), and nonvolatile bits (WPEN, BP1, BP0) retaining their last written values. The EEPROM array is shipped with all FFh (0xFF) data, and WPEN is initially 0 - meaning the WP pin is disabled and software can freely configure protection bits on first use.
AT25080B-MAHL-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 8Kbit
- Memory Organization:
- 1K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT25080B-MAHL-T FAQ
1.How can I place an order for AT25080B-MAHL-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25080B-MAHL-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25080B-MAHL-T reliable?
The price and inventory of AT25080B-MAHL-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25080B-MAHL-T is usually 5 days.
3.What payment methods are accepted for AT25080B-MAHL-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25080B-MAHL-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25080B-MAHL-T?
AT25080B-MAHL-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25080B-MAHL-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25080B-MAHL-T?
For technical support, including AT25080B-MAHL-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25080B-MAHL-T requirements.
6.How does Aetrix verify that AT25080B-MAHL-T is sourced from the original manufacturer or authorized distributors?
All AT25080B-MAHL-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25080B-MAHL-T meets industry standards.
7.What is the process for return or replacement of AT25080B-MAHL-T?
All AT25080B-MAHL-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25080B-MAHL-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25080B-MAHL-T part is unused and in its original packaging.
Return procedure for AT25080B-MAHL-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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