Microchip Technology AT25128-10PC
- Part No.:
- AT25128-10PC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT25128-10PC.pdf
- Description:
- IC EEPROM 128KBIT SPI 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,863
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Product details
Overview
AT25128-10PC from Atmel is a 128 Kbit (16,384 × 8) serial SPI EEPROM in 8-pin SOIC package, operating from 2.7V to 5.5V, supporting 3 MHz clock rate, 64-byte page write, and hardware/software write protection via WP and HOLD pins. It serves as nonvolatile configuration storage in microcontroller-based industrial control modules requiring reliable low-power data retention.
For engineers reviewing the AT25128-10PC datasheet, AT25128-10PC pinout, AT25128-10PC application, or AT25128-10PC equivalent, key selection criteria include VCC range (2.7–5.5 V), SPI Mode 0/3 compatibility, 5 ms typical write cycle time, block write protection granularity (1/4, 1/2, or full array), and industrial temperature rating (–40°C to +85°C).
Technical Context
The AT25128-10PC implements a synchronous slave SPI interface with separate SI (input) and SO (output) lines, MSB-first data transfer, and chip-select–driven command protocol. It uses an 8-bit instruction register with op-codes for WREN, WRITE, READ, RDSR, WRSR, and WRDI.
Internal architecture includes a nonvolatile status register with BP0/BP1 for block protection and WPEN for hardware write protect enable/disable, plus automatic address incrementing during multi-byte reads and page writes. All write cycles are self-timed with no external erase required.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8 bytes); sufficient for firmware parameter tables or calibration data in space-constrained embedded systems. |
| Supply Voltage Range | 2.7 V to 5.5 V; supports dual-rail designs and brown-out tolerant operation across 3.3 V and 5 V logic domains. |
| Max Clock Frequency | 3 MHz (at VCC ≥ 2.7 V); enables fast configuration loading without demanding high-speed MCU peripherals. |
| Write Cycle Time | 5 ms typical; defines minimum interval between successive write commands and impacts system-level latency during updates. |
| Endurance & Retention | 100,000 write cycles / >200 years data retention; meets long-life requirements for field-deployed industrial sensors and controllers. |
| Operating Temperature | –40°C to +85°C; qualified for use in automotive body electronics and industrial PLC I/O modules. |
| ESD Protection | >4000 V HBM; provides robustness against handling and board-level electrostatic discharge events. |
Pinout & Package
AT25128-10PC is housed in an 8-pin EIAJ SOIC (8S2) package, 0.200" wide, with standard gull-wing leads and 1.27 mm pitch. Pin 1 is marked by a notch or dot at the top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select | Active-low enable signal; must be held low during entire SPI transaction; high-impedance SO output when CS is high. |
| 2 (SCK) | Serial Clock Input | Master-generated clock; timing reference for SI sampling and SO output; supports SPI Modes 0 and 3 only. |
| 3 (SI) | Serial Data Input | Receives op-code, address, and data bits MSB-first; ignored during HOLD or when CS is high. |
| 4 (SO) | Serial Data Output | Tri-state output delivering read data or status bits; enters high-Z state when CS goes high or HOLD is asserted. |
| 5 (WP) | Write Protect | Hardware lock for status register writes when WPEN = 1; prevents accidental configuration corruption during power transitions. |
| 6 (HOLD) | Communication Suspend | Pauses ongoing SPI transfer without resetting internal state; allows MCU to service higher-priority interrupts mid-sequence. |
| 7 (GND) | Ground Reference | Primary return path for all digital I/O and supply current; must be low-impedance and decoupled near VCC pin. |
| 8 (VCC) | Power Supply | Single 2.7–5.5 V supply; requires local 0.1 µF ceramic decoupling capacitor placed within 5 mm of the pin. |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode 0 & 3 Support | Ensures interoperability with legacy 6800-series MCUs and modern ARM Cortex-M SPI peripherals without mode translation logic. |
| 64-byte Page Write | Reduces total programming time vs. byte-write-only devices; enables efficient bulk updates of configuration blocks. |
| Block Write Protection | Configurable 1/4, 1/2, or full-array lock via status register; isolates critical boot parameters from runtime overwrites. |
| Hardware + Software Protection | WP pin and WRSR-controlled WPEN bit provide layered security-prevents both physical and firmware-initiated corruption. |
| Industrial Temperature Rating | Validated operation from –40°C to +85°C; eliminates derating concerns in uncontrolled ambient environments like factory floors. |
Applications
| Industrial Sensor Calibration Storage | Automotive Body Control Module (BCM) |
|---|---|
|
Use Scenario: Storing factory-calibrated offset/gain coefficients for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during power-up initialization; read-only during normal operation. Use Value: Eliminates need for external trimming components and enables field recalibration via SPI without hardware modification. |
Use Scenario: Holding seat position memory, mirror angle presets, and lighting configuration in 12 V automotive BCMs. IC Role / Device Role / Timing Role: SPI slave storing user preferences; accessed infrequently but requiring guaranteed retention over 15+ year vehicle life. Use Value: Meets AEC-Q100 stress test requirements and >200-year data retention spec for zero-failure warranty compliance. |
| Medical Infusion Pump Settings | Smart Energy Meter Firmware Parameters |
|
Use Scenario: Securing drug library limits, alarm thresholds, and dosage history logs in Class II medical devices. IC Role / Device Role / Timing Role: Tamper-resistant storage with hardware WP pin tied low; status register locked via WRSR to prevent runtime reconfiguration. Use Value: Supports IEC 62304 software safety classification by preventing unauthorized parameter changes during operation. |
Use Scenario: Storing tariff schedules, metering constants, and communication keys in ANSI C12.19-compliant smart meters. IC Role / Device Role / Timing Role: Secure configuration store with block protection enabled on top quarter (0x3000–0x3FFF) for cryptographic keys. Use Value: Enables secure over-the-air updates while preserving root keys in write-protected memory segment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95128-WMN6TP | Same 128 Kbit density and SOIC-8 package; operates at 1.8–5.5 V; max clock 20 MHz; 1 million endurance cycles. | Better suited for battery-powered IoT nodes needing ultra-low ISB (< 100 nA) and faster writes, but lacks HOLD pin. | Select M95128-WMN6TP when higher speed and lower standby current are critical, and HOLD functionality is not required. |
| 25LC128-I/P | 128 Kbit, PDIP-8 package; 2.5–5.5 V operation; 2 MHz max clock; 1 million endurance; no HOLD pin; WP pin functional only when WPEN set. | Compatible for through-hole prototyping or legacy repair; lower clock rate limits throughput in high-bandwidth logging. | Choose 25LC128-I/P for cost-sensitive, non-HOLD applications where PDIP mounting is preferred and 2 MHz suffices. |
Compared with AT25128-10PC, M95128-WMN6TP offers superior speed and endurance but omits HOLD-critical for interrupt-safe MCU integration-while 25LC128-I/P trades package flexibility and HOLD for broader voltage tolerance and lower unit cost in non-industrial settings.
Availability
AT25128-10PC is available at Aetrix Electronics and suitable for industrial automation, automotive subsystems, and medical device manufacturing requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for AT25128-10PC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT25128-10PC belongs to Atmel's SPI Serial EEPROM product line, designed specifically for robust, low-power, pin-efficient nonvolatile storage in resource-constrained embedded systems across industrial and automotive markets.
FAQ
What is the maximum clock frequency supported by the AT25128-10PC?
The AT25128-10PC supports up to 3 MHz SCK frequency when operating within its 2.7–5.5 V supply range. This value is validated across the full industrial temperature range (–40°C to +85°C) and ensures reliable timing margin for standard SPI peripherals. Exceeding 3 MHz may cause setup/hold violations and data corruption, as confirmed in the AC Characteristics table on page 4 of the official datasheet.
Does the AT25128-10PC require an external erase cycle before writing?
No, the AT25128-10PC does not require a separate erase cycle. All write operations-including byte and page writes-are self-timed and internally manage cell erasure and programming. The device automatically completes erase-and-program sequences during the 5 ms typical write cycle, eliminating firmware overhead and simplifying host driver implementation for AT25128-10PC integration.
How does the HOLD pin function during an active SPI transaction?
The HOLD pin on the AT25128-10PC suspends serial communication without resetting the internal address counter or command state. When asserted low while SCK is low, it places SO in high-impedance and ignores SI inputs until HOLD returns high (also during SCK low). This allows the host MCU to pause AT25128-10PC transfers to service interrupts, then resume seamlessly from the exact bit position.
Can the AT25128-10PC be used in a 1.8 V system?
No-the AT25128-10PC variant is rated for 2.7 V to 5.5 V operation only. While the AT25128 family includes -1.8 suffix parts (e.g., AT25128-10PC-1.8), the AT25128-10PC itself lacks 1.8 V qualification. Using it below 2.7 V risks unreliable read/write behavior and violates Absolute Maximum Ratings; always verify VCC compliance per ordering code suffix for AT25128-10PC.
What protection mechanisms prevent unintended writes to the AT25128-10PC?
The AT25128-10PC employs three layered protections: (1) Write Enable Latch (WREN instruction required before any write), (2) Status register–controlled block protection (BP0/BP1 bits), and (3) Hardware WP pin enforcement when WPEN = 1. All three must be satisfied for a write to succeed-ensuring robust immunity to noise, reset glitches, or firmware bugs during AT25128-10PC operation.
AT25128-10PC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 3 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT25128-10PC FAQ
1.How can I place an order for AT25128-10PC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25128-10PC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25128-10PC reliable?
The price and inventory of AT25128-10PC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25128-10PC is usually 5 days.
3.What payment methods are accepted for AT25128-10PC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25128-10PC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25128-10PC?
AT25128-10PC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25128-10PC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25128-10PC?
For technical support, including AT25128-10PC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25128-10PC requirements.
6.How does Aetrix verify that AT25128-10PC is sourced from the original manufacturer or authorized distributors?
All AT25128-10PC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25128-10PC meets industry standards.
7.What is the process for return or replacement of AT25128-10PC?
All AT25128-10PC units undergo pre-shipment inspection (PSI). If there is an issue with AT25128-10PC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25128-10PC part is unused and in its original packaging.
Return procedure for AT25128-10PC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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