My Inquiry
My Account
Microchip Technology AT25128-10PC-2.7
- Part No.:
- AT25128-10PC-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT25128-10PC-2.7.pdf
- Description:
- IC EEPROM 128KBIT SPI 8DIP
- Quantity:
- Payment:
- Shipping:
Inventory:2,551
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25128-10PC-2.7 from Atmel (now Microchip Technology) is a 128 Kbit SPI serial EEPROM organized as 16,384 × 8-bit words, operating from 2.7V to 5.5V, supporting 3 MHz clock rate and 64-byte page write. It features hardware write protection via WP pin, HOLD for serial suspension, and block-level write protection (1/4, 1/2, or full array). It is used in industrial control systems for parameter storage requiring low-voltage operation and high reliability.
For engineers reviewing the AT25128-10PC-2.7 datasheet, AT25128-10PC-2.7 pinout, AT25128-10PC-2.7 application, or AT25128-10PC-2.7 equivalent, key selection criteria include VCC range (2.7–5.5 V), 8-pin SOIC package compatibility, SPI Mode 0/3 support, 5 ms typical write cycle time, and endurance of 100,000 write cycles - all critical for embedded firmware configuration and calibration data retention.
Technical Context
The AT25128-10PC-2.7 implements a synchronous SPI slave interface with separate SI (input) and SO (output) pins, requiring CS activation and MSB-first data framing. It uses an 8-bit instruction register with op-codes for WREN, WRITE, RDSR, WRSR, and READ, and supports automatic address increment during sequential reads.
Its internal architecture includes a nonvolatile status register with BP0/BP1 bits for block protection and WPEN bit enabling hardware write protection via the WP pin. The HOLD pin suspends ongoing serial transfers without resetting the sequence, and all write cycles are self-timed with no erase prerequisite.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8-bit words) - sufficient for storing boot parameters, calibration coefficients, or device identity in space-constrained designs. |
| Supply Voltage Range | 2.7 V to 5.5 V - enables direct interfacing with 3.3 V and 5 V microcontrollers without level-shifting. |
| Max Clock Frequency | 3 MHz - supports fast configuration loading in real-time systems while maintaining signal integrity on PCB traces. |
| Write Cycle Time | 5 ms typical - defines minimum interval between write commands; impacts firmware update latency and logging throughput. |
| Endurance | 100,000 write cycles - ensures long-term reliability in applications with frequent parameter updates, such as sensor calibration logs. |
| Data Retention | >200 years - guarantees persistent storage of critical settings across product lifetime without refresh. |
| Block Protection | Configurable 1/4, 1/2, or full array - allows secure locking of factory defaults or security keys while permitting runtime updates to user sectors. |
Pinout & Package
AT25128-10PC-2.7 is housed in an 8-pin EIAJ SOIC package (0.200" wide), with standard JEDEC-compliant footprint and 1.27 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select | Active-low enable signal; must be low to accept instructions; high impedance on SO when deasserted. |
| 2 (SCK) | Serial Clock Input | Synchronizes all data transfers; supports SPI Modes 0 and 3; max 3 MHz frequency. |
| 3 (SI) | Serial Data Input | Receives op-codes, addresses, and write data; MSB-first, sampled on SCK rising edge (Mode 0). |
| 4 (WP) | Write Protect | Hardware lock for status register and protected memory blocks when WPEN = 1 and WP = low. |
| 5 (HOLD) | Serial Hold | Pauses active SPI communication without resetting sequence; requires SCK low during assertion. |
| 6 (GND) | Ground Reference | Return path for VCC and all I/O signals; must be low-impedance to minimize noise coupling into SO/SI. |
| 7 (VCC) | Power Supply | 2.7–5.5 V supply; decoupling capacitor (0.1 µF) required near pin to suppress switching transients. |
| 8 (SO) | Serial Data Output | Tri-state output delivering read data or status bits; high-impedance when CS high or during HOLD. |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode Compatibility | Supports both Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1), ensuring interoperability with diverse MCU SPI peripherals. |
| Page Write Capability | 64-byte page write reduces transaction overhead vs. byte writes - cuts firmware update time by up to 64× for contiguous data. |
| Multi-Level Block Protection | BP0/BP1 bits allow selective locking of top 1/4, top 1/2, or entire memory - isolates factory firmware from field updates. |
| Hardware + Software Write Protection | WP pin + WRSR-controlled WPEN bit provide dual-layer defense against accidental or malicious writes to critical registers. |
| Extended Temperature Support | Qualified for industrial range (−40°C to +85°C), enabling use in motor drives, power supplies, and outdoor instrumentation. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed at startup and during runtime reconfiguration; operates under 2.7–5.5 V supply with immunity to brown-out events. Use Value: Enables field-upgradable control logic without requiring external backup batteries or complex FRAM management. |
Use Scenario: Retaining sensor offset/gain coefficients, patient-specific therapy profiles, and regulatory audit logs in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure, tamper-resistant data vault with block write protection preventing overwrite of calibrated values during routine operation. Use Value: Meets IEC 62304 Class B software safety requirements through guaranteed 200-year data retention and 100K-cycle endurance. |
| Automotive Body Control Module (BCM) | Smart Energy Meter Firmware Settings |
|
Use Scenario: Holding seat/mirror position presets, lighting profiles, and CAN node configuration in automotive BCMs operating across −40°C to +85°C. IC Role / Device Role / Timing Role: SPI EEPROM interfaced directly to 32-bit ARM Cortex-M MCU; withstands automotive load dump and cold crank conditions. Use Value: Eliminates need for external voltage supervisors or write-protection logic, reducing BOM count and board area. |
Use Scenario: Storing tariff schedules, metering constants, and utility authentication keys in ANSI C12.22-compliant smart meters exposed to wide ambient temperature swings. IC Role / Device Role / Timing Role: Low-power serial memory with 2 µA standby current at 2.7 V - extends battery life in AMI endpoint devices. Use Value: Supports secure over-the-air (OTA) updates via write-enable/disable sequencing and status register verification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95128-WMN6TP | 128 Kbit SPI EEPROM, 2.5–5.5 V supply, 20 MHz max clock, 5 ms write cycle, 8-pin SOIC (same footprint). | Higher speed (20 MHz vs. 3 MHz) and broader VCC range; lacks HOLD pin and has different status register layout. | Select when higher throughput is needed and HOLD functionality is not required; verify timing and protection register compatibility. |
| 25AA128-I/P | 128 Kbit SPI EEPROM, 1.8–5.5 V supply, 10 MHz max clock, 5 ms write cycle, 8-pin PDIP/SOIC options. | Wider low-voltage range (1.8 V), no HOLD pin, different pinout (SO on pin 2, SI on pin 5), same WP/CS/SCK/GND/VCC assignment. | Choose for ultra-low-voltage systems (<2.7 V); requires PCB layout revision due to SI/SO pin swap versus AT25128-10PC-2.7. |
Compared with M95128-WMN6TP and 25AA128-I/P, AT25128-10PC-2.7 offers unique HOLD functionality for interrupt-safe SPI transactions and consistent pinout across voltage variants - critical for legacy design reuse and deterministic real-time behavior in industrial firmware.
Availability
AT25128-10PC-2.7 is available at Aetrix Electronics and suitable for industrial control systems, medical diagnostics equipment, automotive body electronics, and smart energy metering requiring stable component supply and long-term obsolescence management.
Supply support for AT25128-10PC-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation, now part of Microchip Technology, is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial, automotive, and consumer markets.
The AT25128-10PC-2.7 belongs to Atmel's SPI Serial EEPROM product line, designed specifically for reliable, low-power, pin-efficient nonvolatile storage in resource-constrained embedded systems where SPI interface simplicity and robust write protection are essential.
FAQ
What is the operating voltage range of the AT25128-10PC-2.7?
The AT25128-10PC-2.7 operates from 2.7 V to 5.5 V, making it compatible with both 3.3 V and 5 V logic families without level translation. This dual-voltage capability is explicitly defined in its ordering code suffix "-2.7" and confirmed in DC Characteristics tables, where VCC2 min = 2.7 V and max = 5.5 V.
Does the AT25128-10PC-2.7 support SPI Mode 0 and Mode 3?
Yes, the AT25128-10PC-2.7 supports both SPI Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 1), as stated in its Features section and verified in timing diagrams. This dual-mode support ensures interoperability with a broad range of microcontrollers including AVR, PIC, and ARM-based devices.
How does the HOLD pin function on the AT25128-10PC-2.7?
The HOLD pin on the AT25128-10PC-2.7 suspends ongoing SPI communication without resetting the internal address counter or command state. When asserted low while SCK is low, it places SO in high-impedance and ignores SI inputs; resuming requires bringing HOLD high while SCK remains low. This enables deterministic pause/resume in multi-master or interrupt-driven systems.
What is the maximum clock frequency supported by the AT25128-10PC-2.7?
The AT25128-10PC-2.7 supports a maximum SCK frequency of 3 MHz across its full 2.7–5.5 V operating range, as specified in AC Characteristics tables under fSCK. This limit applies regardless of temperature grade and is validated for reliable data sampling and setup/hold timing compliance.
Can the AT25128-10PC-2.7 be used in industrial temperature applications?
Yes, the AT25128-10PC-2.7 is qualified for the industrial temperature range of −40°C to +85°C, as indicated by the "I" suffix in alternate ordering codes (e.g., AT25128-10PI-2.7) and confirmed in Absolute Maximum Ratings and DC Characteristics test conditions. Its packaging and process ensure stable operation across this range.
AT25128-10PC-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 3 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT25128-10PC-2.7 FAQ
1.How can I place an order for AT25128-10PC-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25128-10PC-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25128-10PC-2.7 reliable?
The price and inventory of AT25128-10PC-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25128-10PC-2.7 is usually 5 days.
3.What payment methods are accepted for AT25128-10PC-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25128-10PC-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25128-10PC-2.7?
AT25128-10PC-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25128-10PC-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25128-10PC-2.7?
For technical support, including AT25128-10PC-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25128-10PC-2.7 requirements.
6.How does Aetrix verify that AT25128-10PC-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25128-10PC-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25128-10PC-2.7 meets industry standards.
7.What is the process for return or replacement of AT25128-10PC-2.7?
All AT25128-10PC-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25128-10PC-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25128-10PC-2.7 part is unused and in its original packaging.
Return procedure for AT25128-10PC-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25128-10PC-2.7 Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
