Microchip Technology AT25128-10UI-2.7
- Part No.:
- AT25128-10UI-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-VFBGA
- Datasheet:
-
AT25128-10UI-2.7.pdf
- Description:
- IC EEPROM 128KBIT SPI 8DBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,380
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25128-10UI-2.7 from Microchip Technology (formerly Atmel) is a 128 Kbit SPI serial EEPROM organized as 16,384 × 8-bit memory array, operating at 2.7V–5.5V supply, supporting 3 MHz clock rate and 64-byte page write. It features hardware write protection via WP pin, HOLD for serial suspend, and block protection for 1/4, 1/2 or full memory array - deployed in industrial control modules requiring nonvolatile parameter storage with low-power operation.
For engineers reviewing the AT25128-10UI-2.7 datasheet, AT25128-10UI-2.7 pinout, AT25128-10UI-2.7 application, or AT25128-10UI-2.7 equivalent, key selection criteria include verified 2.7V–5.5V operation, SOIC-8 package compatibility, SPI Mode 0/3 support, 100,000 write endurance, and integrated hardware/software data protection architecture.
Technical Context
The AT25128-10UI-2.7 implements a synchronous SPI slave interface with separate SI (input) and SO (output) pins, requiring CS-driven selection and MSB-first data framing. Its internal instruction register accepts op-codes including WREN, WRDI, RDSR, WRSR, READ, and WRITE - all validated under -40°C to +85°C industrial temperature range.
Block write protection is controlled nonvolatively via BP0/BP1 bits in the status register, enabling selective locking of top 1/4 (0x3000–0x3FFF), top 1/2 (0x2000–0x3FFF), or entire (0x0000–0x3FFF) memory segments. The WP pin interacts with the WPEN bit to enable hardware-level status register lockout when both are asserted.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8-bit words) - sufficient for firmware configuration tables, calibration data, or device identity storage in space-constrained embedded systems. |
| Supply Voltage Range | 2.7V to 5.5V - supports direct interfacing with 3.3V microcontrollers and legacy 5V logic without level-shifting. |
| Max Clock Frequency | 3 MHz - enables fast parameter read/write cycles while maintaining timing margin across industrial temperature range. |
| Write Endurance | 100,000 cycles - ensures reliable reprogramming over product lifetime in field-updatable devices like smart sensors or PLC I/O modules. |
| Data Retention | >200 years - guarantees long-term integrity of stored calibration coefficients or security keys without refresh. |
| Page Write Size | 64 bytes - optimizes burst writes for contiguous configuration blocks while minimizing bus occupancy time. |
| Operating Temperature | -40°C to +85°C - qualified for deployment in automotive body controllers, industrial HMIs, and outdoor metering equipment. |
Pinout & Package
AT25128-10UI-2.7 is housed in an 8-pin EIAJ SOIC (8S2) package, 0.200" wide, with standard gull-wing leads and JEDEC-compliant footprint. Pin 1 is marked by index notch or dot; package meets RoHS requirements and supports reflow soldering per J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal - must be held low during full SPI transaction; high impedance on SO occurs when CS is high. |
| SCK | Serial Clock | Master-generated clock input - synchronizes all SI/SO data transfers; supports Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). |
| SI | Serial Data Input | Unidirectional command/address/data input path - receives op-codes, addresses, and write data MSB-first. |
| SO | Serial Data Output | Unidirectional read-data output - drives data only when CS is low and transaction is active; high-Z otherwise. |
| WP | Write Protect | Hardware lock for status register - when WPEN=1 and WP=low, prevents modification of BP0/BP1/WPEN bits and protected memory regions. |
| HOLD | Serial Suspend | Pauses ongoing SPI communication without resetting sequence - allows host MCU to service higher-priority interrupts mid-transaction. |
| GND | Ground Reference | Primary return path for VCC and I/O signals - requires low-impedance connection to minimize noise coupling into sensitive EEPROM operations. |
| VCC | Power Supply | Single-supply input - powers internal logic and charge pump; bypass capacitor (0.1 µF) required within 10 mm of pin per layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed write cycle | 5 ms typical - eliminates need for external timing control or polling delay; host can issue next command after tWC completion. |
| Block write protection | Configurable 1/4, 1/2 or full-array lock - prevents accidental overwrite of critical boot parameters or security credentials during field updates. |
| Hardware + software protection | WP pin + WRSR instruction - enables layered security: physical lockout during board assembly and dynamic lock/unlock via firmware. |
| Industrial temperature grade | -40°C to +85°C operation - validated for use in motor drives, HVAC controllers, and factory automation where ambient thermal stress is significant. |
| ESD robustness | >4000V HBM - reduces risk of latch-up or parametric shift during handling or system integration in unshielded environments. |
Applications
| Industrial Sensor Calibration Storage | PLC Configuration Memory |
|---|---|
Use Scenario: Storing temperature-compensated offset/gain coefficients for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile parameter repository accessed during power-up initialization and runtime recalibration routines. Use Value: Enables field-replaceable sensor modules with persistent calibration data, eliminating manual re-trimming after module swap. |
Use Scenario: Holding user-defined I/O mapping, scan cycle timing, and alarm thresholds in compact PLCs deployed in manufacturing lines. IC Role / Device Role / Timing Role: Configuration database updated via HMI or engineering software, retained across power cycles and firmware upgrades. Use Value: Supports zero-downtime configuration changes without requiring EEPROM reprogramming tools onsite. |
| Smart Meter Firmware Parameters | Automotive Body Control Module Settings |
Use Scenario: Storing tariff schedules, pulse constants, and tamper-event logs in ANSI C12.22-compliant electricity meters. IC Role / Device Role / Timing Role: Secure, write-protected memory segment for regulatory-critical data with audit trail capability. Use Value: Meets ANSI/IEEE C12.19 data retention and integrity requirements for 20+ year field life. |
Use Scenario: Retaining seat position presets, mirror angles, and lighting profiles in automotive BCMs across ignition cycles. IC Role / Device Role / Timing Role: Low-power, fast-access storage for user preferences synchronized with CAN bus wake events. Use Value: Achieves sub-100ms recall of settings after key-on, leveraging 2.7V operation compatible with vehicle battery brownout conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95128-DRMN6TP/K | STMicroelectronics 128 Kbit SPI EEPROM; same 8-pin SOIC package, 2.5–5.5V range, 20 MHz max clock, but lacks HOLD pin and uses different status register layout. | Supports higher-speed reads but cannot pause ongoing transactions - unsuitable where host MCU interrupt latency exceeds 5 ms. | Select when maximum throughput is prioritized over serial suspend capability and pin compatibility is confirmed. |
| BR24G128FJ-WE2 | Rohm 128 Kbit SPI EEPROM; 1.7–5.5V operation, 10 MHz clock, built-in write protect via WPEN bit, but only offers 1/2 or full-array protection (no 1/4 option). | Broader voltage range supports single-cell Li-ion backup, but reduced granularity limits partial configuration locking in multi-zone systems. | Choose for battery-powered edge nodes needing ultra-low standby current (0.1 µA) and wider VCC flexibility. |
Compared with M95128-DRMN6TP/K and BR24G128FJ-WE2, AT25128-10UI-2.7 uniquely delivers HOLD functionality for deterministic interrupt handling, precise 1/4-array protection for modular firmware partitioning, and verified -40°C to +85°C performance without derating - making it optimal for industrial real-time control applications demanding both reliability and functional granularity.
Availability
AT25128-10UI-2.7 is available at Aetrix Electronics and suitable for industrial sensor calibration storage, PLC configuration memory, smart meter firmware parameters, and automotive body control module settings requiring stable component supply and long-term lifecycle assurance.
Supply support for AT25128-10UI-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full technical and manufacturing continuity for the AT25xxx EEPROM family, delivering high-reliability nonvolatile memory solutions for mission-critical embedded systems.
The AT25xxx series was designed specifically for industrial and automotive applications requiring robust SPI EEPROMs with flexible voltage operation, hardware write protection, and extended temperature qualification - addressing needs in programmable logic, sensor interfaces, and control subsystems.
FAQ
What is the maximum clock frequency supported by the AT25128-10UI-2.7?
The AT25128-10UI-2.7 supports a maximum SCK clock frequency of 3 MHz across its full 2.7V–5.5V supply range and -40°C to +85°C operating temperature. This value is specified in the AC Characteristics table under fSCK parameter and applies to both read and write operations. Exceeding this limit may cause data corruption or command rejection during SPI transactions involving the AT25128-10UI-2.7.
Does the AT25128-10UI-2.7 require an external pull-up resistor on the SO pin?
No, the AT25128-10UI-2.7 does not require an external pull-up on the SO pin. Its SO output is actively driven high or low during valid read cycles and enters high-impedance state when CS is high or during HOLD assertion. External pull-ups may interfere with signal integrity and are explicitly omitted in Atmel/Microchip reference designs for the AT25128-10UI-2.7.
How is block write protection configured on the AT25128-10UI-2.7?
Block write protection on the AT25128-10UI-2.7 is configured by writing to the status register using the WRSR instruction. Bits BP1 and BP0 determine protection level: 00 = none, 01 = top 1/4 (0x3000–0x3FFF), 10 = top 1/2 (0x2000–0x3FFF), 11 = full array (0x0000–0x3FFF). These bits are nonvolatile and retain setting across power cycles, ensuring persistent protection for the AT25128-10UI-2.7.
Can the AT25128-10UI-2.7 operate reliably at 1.8V?
No, the AT25128-10UI-2.7 is rated for 2.7V–5.5V operation only. While the AT25128 family includes a -1.8 suffix variant (e.g., AT25128-10UI-1.8), the -2.7 suffix in AT25128-10UI-2.7 explicitly denotes the 2.7V–5.5V voltage grade. Operating the AT25128-10UI-2.7 below 2.7V risks incomplete write cycles, status register corruption, or undefined behavior during SPI communication.
What is the function of the HOLD pin on the AT25128-10UI-2.7?
The HOLD pin on the AT25128-10UI-2.7 suspends ongoing SPI communication without resetting the internal address counter or command state. When asserted low while SCK is low, it places SO in high-impedance and ignores SI inputs, allowing the host MCU to service interrupts. Resuming requires bringing HOLD high while SCK remains low - a deterministic mechanism preserved across all AT25128-10UI-2.7 transactions.
AT25128-10UI-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-VFBGA
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 3 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-dBGA (3.73x2.21)
AT25128-10UI-2.7 FAQ
1.How can I place an order for AT25128-10UI-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25128-10UI-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25128-10UI-2.7 reliable?
The price and inventory of AT25128-10UI-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25128-10UI-2.7 is usually 5 days.
3.What payment methods are accepted for AT25128-10UI-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25128-10UI-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25128-10UI-2.7?
AT25128-10UI-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25128-10UI-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25128-10UI-2.7?
For technical support, including AT25128-10UI-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25128-10UI-2.7 requirements.
6.How does Aetrix verify that AT25128-10UI-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25128-10UI-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25128-10UI-2.7 meets industry standards.
7.What is the process for return or replacement of AT25128-10UI-2.7?
All AT25128-10UI-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25128-10UI-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25128-10UI-2.7 part is unused and in its original packaging.
Return procedure for AT25128-10UI-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25128-10UI-2.7 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

