My Inquiry
My Account
Microchip Technology AT25128AN-10SU-2.7
- Part No.:
- AT25128AN-10SU-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25128AN-10SU-2.7.pdf
- Description:
- IC EEPROM 128KBIT SPI 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,506
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25128AN-10SU-2.7 from Microchip Technology (formerly Atmel) is a 128 Kbit SPI serial EEPROM organized as 16,384 × 8 bits, operating from 2.7V to 5.5V, supporting 20 MHz clock rate at 5V, featuring 64-byte page write, hardware/software write protection, and industrial temperature range (−40°C to +85°C). It serves as nonvolatile configuration storage in microcontroller-based embedded systems requiring low-power, reliable data retention.
For engineers reviewing the AT25128AN-10SU-2.7 datasheet, AT25128AN-10SU-2.7 pinout, AT25128AN-10SU-2.7 application, or AT25128AN-10SU-2.7 equivalent, key selection criteria include SPI Mode 0/3 compatibility, 5 ms max self-timed write cycle, block write protection granularity (1/4, 1/2, or full array), VCC voltage range compliance, and SOIC-8 package mechanical fit for space-constrained PCB layouts.
Technical Context
The AT25128AN-10SU-2.7 implements a synchronous SPI slave interface with separate SI (input) and SO (output) pins, supporting MSB-first transmission and op-code–driven command execution (e.g., WREN, WRITE, RDSR). It uses an internal 8-bit instruction register and requires CS low to initiate communication.
Its architecture includes a nonvolatile status register with BP0/BP1 bits for block protection, WPEN bit enabling hardware write protection via the WP pin, and RDY/WEN flags for real-time readiness and write-enable state monitoring - all accessible via RDSR/WRSR instructions without interrupting ongoing operations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8), sufficient for firmware calibration tables or device configuration profiles in resource-limited MCUs. |
| Supply Voltage Range | 2.7V to 5.5V - supports direct interfacing with 3.3V and 5V logic domains without level shifting. |
| Max Clock Frequency | 20 MHz at VCC = 5.0V - enables fast bulk read/write for time-critical parameter updates. |
| Write Cycle Time | 5 ms maximum - defines worst-case latency for persistent data commit; no external erase required. |
| Endurance & Retention | 1 million write cycles and >100 years data retention - suitable for long-life industrial deployments with infrequent but critical writes. |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade operation without derating in ambient-temperature-variable environments. |
| Interface Protocol | SPI Modes 0 (CPOL=0, CPHA=0) and 3 (CPOL=1, CPHA=1) - ensures interoperability with diverse host controllers including ARM Cortex-M and legacy 8051 derivatives. |
Pinout & Package
AT25128AN-10SU-2.7 is housed in an 8-lead JEDEC SOIC package (package code 8S1), 0.150" wide body, RoHS-compliant and lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be held low during entire SPI transaction to assert device presence on bus. |
| SCK | Serial Clock | Input-only clock input; synchronizes SI data sampling and SO data output; determines max throughput (20 MHz @ 5V). |
| SI | Serial Data Input | Unidirectional input for op-codes, addresses, and write data; MSB-first format required per SPI specification. |
| SO | Serial Data Output | Unidirectional output for read data and status register contents; high-impedance when CS is high or HOLD is active. |
| GND | Ground Reference | Primary return path for VCC current and digital I/O reference; must be low-impedance to minimize noise coupling into SPI signals. |
| VCC | Power Supply | Single supply input (2.7–5.5V); powers internal logic, memory array, and I/O buffers; bypass capacitor recommended. |
| WP | Write Protect | Hardware lock for status register and protected memory blocks when WPEN=1 and WP=low; prevents accidental overwrites. |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer without resetting sequence; allows host to service higher-priority interrupts mid-transaction. |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte Page Write | Enables efficient multi-byte programming within a single write cycle, reducing total commit time versus byte-by-byte writes. |
| Block Write Protection | Configurable via status register to protect top 1/4, top 1/2, or entire memory array - secures boot code or calibration constants. |
| Hardware + Software Protection | Combines WP pin control (hardware) with WREN/WRDI instructions (software) for layered data integrity assurance. |
| Self-timed Internal Write | Eliminates need for external timing control or polling delay; host can issue RDSR to check RDY bit for completion. |
| Industrial Temperature Range | Validated operation from −40°C to +85°C ensures reliability in factory automation, metering, and outdoor electronics. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during power-up and runtime reconfiguration via SPI from ARM-based controller. Use Value: Ensures deterministic startup behavior and field-updatable settings without requiring battery-backed SRAM or external flash management. |
Use Scenario: Retaining sensor offset/gain coefficients and regulatory audit logs in portable diagnostic equipment subject to periodic recalibration. IC Role / Device Role / Timing Role: Secure, tamper-resistant data vault accessed only during calibration mode using authenticated SPI commands. Use Value: Meets IEC 62304 data integrity requirements with 1M endurance and >100-year retention for lifetime device traceability. |
| Smart Energy Meter Firmware Parameters | Automotive Body Control Module Settings |
|
Use Scenario: Holding tariff schedules, metering constants, and cryptographic keys in ANSI C12.22–compliant electricity meters. IC Role / Device Role / Timing Role: SPI-connected configuration store interfaced to TI MSP430 or Renesas RL78 MCU during secure boot and OTA update verification. Use Value: Block protection prevents unauthorized modification of billing-critical parameters while allowing safe field updates to non-protected sectors. |
Use Scenario: Saving seat position memory, mirror presets, and lighting profiles in 12V automotive BCMs operating across extended temperature ranges. IC Role / Device Role / Timing Role: Low-voltage EEPROM (2.7–5.5V) directly powered from vehicle's regulated 3.3V rail, accessed during ignition-on initialization. Use Value: Eliminates need for external voltage translators and supports cold-cranking down to 2.7V while maintaining data integrity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95128-DRMN6TP/K | 128 Kbit SPI EEPROM, 1.8–5.5V supply, 20 MHz max, SOIC-8, but lacks HOLD pin and uses different status register layout. | No HOLD functionality limits use in interrupt-driven hosts; different BP bit mapping requires firmware adaptation. | Select when HOLD is unused and existing software can accommodate alternate status register definitions. |
| BR24G128FJ-WE2 | 128 Kbit I²C EEPROM, 1.7–5.5V, 1 MHz max, TSSOP-8; uses two-wire interface and has built-in write-cycle suspend. | I²C interface reduces pin count but halves max throughput vs. SPI; no native block protection - relies on software locking. | Prefer for designs prioritizing pin count reduction over speed and where I²C infrastructure already exists. |
Compared with M95128-DRMN6TP/K and BR24G128FJ-WE2, the AT25128AN-10SU-2.7 uniquely delivers HOLD-assisted interrupt tolerance, configurable block protection, and SPI Mode 0/3 flexibility - making it optimal for deterministic, high-speed, and security-sensitive embedded configurations.
Availability
AT25128AN-10SU-2.7 is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, smart energy meters, and automotive body control modules requiring stable component supply across multi-year production cycles.
Supply support for AT25128AN-10SU-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT25xxx family of serial EEPROMs.
The AT25128AN-10SU-2.7 belongs to Microchip's SPI serial EEPROM product line, designed specifically for robust, low-power, pin-efficient nonvolatile storage in industrial, medical, and infrastructure applications where data integrity and long-term reliability are critical.
FAQ
What is the maximum clock frequency supported by the AT25128AN-10SU-2.7?
The AT25128AN-10SU-2.7 supports up to 20 MHz SCK frequency when VCC = 5.0V. At lower voltages (2.7V–3.6V), the maximum rated clock frequency drops to 10 MHz, and at 1.8V operation (not applicable to this -2.7 variant), it is 5 MHz. These values are specified in Table 1-3 of the datasheet and reflect guaranteed timing margins under industrial temperature conditions.
Does the AT25128AN-10SU-2.7 support both SPI Mode 0 and Mode 3?
Yes, the AT25128AN-10SU-2.7 explicitly supports SPI Modes 0 (CPOL = 0, CPHA = 0) and 3 (CPOL = 1, CPHA = 1), as stated in the Features section. The device operates as a slave with separate SI/SO lines and MSB-first data framing. Mode selection is handled entirely by the host controller; no internal configuration is required to switch between them.
How does the write protection mechanism work on the AT25128AN-10SU-2.7?
The AT25128AN-10SU-2.7 implements dual-layer write protection: software-based via WREN/WRDI instructions and hardware-based via the WP pin. When WPEN = 1 in the status register and WP is pulled low, writes to the status register and protected memory blocks are blocked. Block protection levels (none, top 1/4, top 1/2, or full array) are set using BP0/BP1 bits, as defined in Table 3-4.
What package type is used for the AT25128AN-10SU-2.7?
The AT25128AN-10SU-2.7 uses an 8-lead JEDEC SOIC package (package code 8S1), 0.150" wide body, with lead-free and halogen-free construction. This is confirmed in the Ordering Information table (page 15) and matches the pin diagram labeled "8-lead SOIC" in the datasheet. It is not PDIP, TSSOP, dBGA2, or SAP.
Is the AT25128AN-10SU-2.7 suitable for automotive applications?
No - the AT25128AN-10SU-2.7 is specified for industrial temperature range (−40°C to +85°C) and is not qualified to AEC-Q100 standards. While it may function in some automotive subsystems, Microchip's official documentation states "Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life," and automotive use is explicitly excluded unless designated with an "A" suffix (e.g., AT25128A-W1.8-11).
AT25128AN-10SU-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25128AN-10SU-2.7 FAQ
1.How can I place an order for AT25128AN-10SU-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25128AN-10SU-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25128AN-10SU-2.7 reliable?
The price and inventory of AT25128AN-10SU-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25128AN-10SU-2.7 is usually 5 days.
3.What payment methods are accepted for AT25128AN-10SU-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25128AN-10SU-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25128AN-10SU-2.7?
AT25128AN-10SU-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25128AN-10SU-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25128AN-10SU-2.7?
For technical support, including AT25128AN-10SU-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25128AN-10SU-2.7 requirements.
6.How does Aetrix verify that AT25128AN-10SU-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25128AN-10SU-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25128AN-10SU-2.7 meets industry standards.
7.What is the process for return or replacement of AT25128AN-10SU-2.7?
All AT25128AN-10SU-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25128AN-10SU-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25128AN-10SU-2.7 part is unused and in its original packaging.
Return procedure for AT25128AN-10SU-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25128AN-10SU-2.7 Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
