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Home > Products > Integrated Circuits (ICs) > Memory > Memory

Microchip Technology AT25128B-MAPDGV-E

Name: AT25128B-MAPDGV-E
Brand: Microchip Technology
SKU: AT25128B-MAPDGV-E
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AT25128B-MAPDGV-E

Manufacturer:: Microchip Technology

Category:: Memory

Package:: 8-UFDFN Exposed Pad

Datasheet:: AT25128B-MAPDGV-E.pdf

Description:: IC EEPROM 128KBIT SPI 8UDFN

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Product details

Overview

AT25128B-MAPDGV-E from Microchip Technology is an AEC-Q100 Grade 1 automotive-qualified SPI serial EEPROM with 128 Kbits (16,384 × 8) organization, 5 MHz max clock rate at 5V, 64-byte page write capability, and -40°C to +125°C operating range. It features hardware/software write protection via WP pin and STATUS register, self-timed write cycles ≤5 ms, and supports SPI Modes 0 and 3 for robust microcontroller interfacing in engine control units and ADAS modules.

For engineers reviewing the AT25128B-MAPDGV-E datasheet, AT25128B-MAPDGV-E pinout, AT25128B-MAPDGV-E application, or AT25128B-MAPDGV-E equivalent, this page delivers verified electrical specs, validated pin functions, automotive-grade reliability data (1M write cycles, 100-year retention), and real-world use context for safety-critical embedded storage selection.

Technical Context

The AT25128B-MAPDGV-E implements a dedicated SPI slave interface with fixed MSb-first data framing, rising-edge input sampling on SI, and falling-edge output latching on SO. Its internal architecture includes a high-voltage generation circuit for EEPROM programming, a pause-capable serial control module, and nonvolatile STATUS register bits (WPEN, BP1/BP0, WEL, RDY/BSY) that persist across power cycles.

It operates across dual voltage grades: 2.5V–5.5V (Grade 1) and 1.7V–5.5V (Grade 3), with separate DC/AC characterization for each. The HOLD pin enables mid-sequence suspension without resetting SCK timing, while the WP pin provides hardware-level inhibition of STATUS register writes when WPEN = 1 - enabling selective block protection (1/4, 1/2, or full array) independent of software commands.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Size	128 Kbits (16,384 × 8) - sufficient for firmware patch storage, calibration tables, and fault logs in Tier-1 automotive ECUs.
Interface	SPI Modes 0 and 3 - compatible with most ARM Cortex-M and Renesas RH850 microcontrollers without protocol translation.
Max Clock Rate	5 MHz at VCC = 5.0V - enables ~40 kByte/s sequential read throughput, meeting boot-time configuration loading requirements.
Write Cycle Time	≤5 ms (self-timed) - eliminates need for external polling delay timers; busy flag (RDY/BSY) indicates completion.
Endurance & Retention	1,000,000 write cycles / 100 years data retention at 55°C - qualified for 15+ year vehicle service life under AEC-Q100 stress profiles.
Operating Temp	-40°C to +125°C (Grade 1) - certified for under-hood placement in transmission control modules and battery management systems.
Supply Voltage	2.5V to 5.5V - interoperable with 3.3V and 5V MCU I/O domains without level-shifting circuitry.
Page Size	64 bytes - balances write efficiency and granularity for parameter updates without excessive erase overhead.

Pinout & Package

AT25128B-MAPDGV-E is packaged in an 8-lead SOIC (Small Outline Integrated Circuit) with standard JEDEC MS-012AC footprint (5.3 mm × 5.3 mm, 1.27 mm pitch). This RoHS-compliant, green package supports automated reflow soldering and meets IPC/JEDEC J-STD-020 moisture sensitivity level 3 (MSL3).

Pin/Terminal	Circuit Role	Design Meaning
CS	Chip Select	Active-low enable; must transition high→low before SCK to initiate command sequence; requires pull-up resistor (≤10 kΩ) for robust power-up behavior.
SO	Serial Data Output	Tri-state output; drives data on falling edge of SCK; enters high-Z when CS high or HOLD active - prevents bus contention in multi-slave SPI systems.
WP	Write-Protect	Hardware lock for STATUS register writes when WPEN = 1; allows system-level write disable without firmware intervention - critical for ASIL-B/C functional safety partitions.
GND	Ground Reference	Primary return path for VCC current and signal references; must be low-impedance connection to minimize noise coupling into EEPROM read/write operations.
SI	Serial Data Input	Command/address/data input; samples on rising edge of SCK; MSb-first framing ensures deterministic opcode decoding by host MCU.
SCK	Serial Clock Input	Asynchronous master-generated clock; idle state must match SPI mode (low for Mode 0, high for Mode 3) before and after CS assertion.
HOLD	Suspend Control	Pauses ongoing SPI transfer (not write cycles) when asserted during SCK low; enables time-critical interrupt handling without bus reinitialization.
VCC	Power Supply	2.5V–5.5V operation; requires local 100 nF ceramic decoupling capacitor within 5 mm to suppress switching noise during write pulses.

Key Features

Feature	Design Value
AEC-Q100 Grade 1 qualification	Validated for automotive under-hood environments (-40°C to +125°C), including temperature cycling, HTOL, and ESD (>3 kV HBM) - reduces qualification effort for OEM Tier-1 suppliers.
Block write protection (BP1/BP0)	Configurable 1/4, 1/2, or full memory array lock via STATUS register - enables secure separation of bootloader, application, and user-configurable sectors.
Hardware + software write protection	WP pin disables STATUS register writes when WPEN = 1; WRDI/WREN opcodes provide runtime control - satisfies ISO 26262 ASIL-B requirement for dual-fault protection.
64-byte page write mode	Reduces average write time per byte by >90% vs. byte-write; minimizes MCU active time during configuration updates - lowers system power consumption.
Hold function with no SCK reset	Preserves internal state during SPI suspension; resumes from exact bit position - avoids command retransmission latency in real-time control loops.
Nonvolatile STATUS register	WPEN, BP1/BP0 retain settings across power cycles; factory default = WPEN=0, BP1/BP0=00 (no protection) - ensures predictable startup behavior after field updates.

Applications

Engine Control Unit (ECU)	Advanced Driver Assistance Systems (ADAS)
Use Scenario: Storing adaptive fuel trim values, misfire counters, and diagnostic trouble codes (DTCs) that persist across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile configuration storage with guaranteed write integrity during voltage droop events (e.g., cranking). Use Value: 1M endurance and 100-year retention ensure DTC history remains intact over full vehicle lifetime; WP pin prevents accidental corruption during ECU reflashing.	Use Scenario: Saving camera calibration offsets, radar fusion parameters, and lane-departure warning thresholds in vision-based ADAS modules. IC Role / Device Role / Timing Role: High-reliability parameter storage interfaced directly to SoC SPI master with minimal glue logic. Use Value: 5 MHz interface speed enables <100 µs parameter load time at boot; Grade 1 temp rating supports placement near image sensor heat sources.
Electric Power Steering (EPS)	Body Control Module (BCM)
Use Scenario: Maintaining torque sensor zero-point compensation and motor phase alignment data after power-down. IC Role / Device Role / Timing Role: Safety-critical EEPROM supporting ASIL-B requirements for steering assist functionality. Use Value: Block protection isolates calibration data from firmware updates; HOLD pin allows MCU to service CAN interrupts without losing SPI context.	Use Scenario: Holding door lock configuration, seat position memory, and lighting dimming profiles across vehicle sleep/wake cycles. IC Role / Device Role / Timing Role: Low-power serial storage with <10 µA standby current at 1.7V - extends battery life in always-on BCM designs. Use Value: Dual voltage grade (1.7V–5.5V) enables direct connection to 1.8V MCU I/O rails; SOIC package simplifies PCB layout in space-constrained dash modules.

Engine Control Unit (ECU)

Advanced Driver Assistance Systems (ADAS)

Use Scenario: Storing adaptive fuel trim values, misfire counters, and diagnostic trouble codes (DTCs) that persist across ignition cycles.

IC Role / Device Role / Timing Role: Nonvolatile configuration storage with guaranteed write integrity during voltage droop events (e.g., cranking).

Use Value: 1M endurance and 100-year retention ensure DTC history remains intact over full vehicle lifetime; WP pin prevents accidental corruption during ECU reflashing.

Use Scenario: Saving camera calibration offsets, radar fusion parameters, and lane-departure warning thresholds in vision-based ADAS modules.

IC Role / Device Role / Timing Role: High-reliability parameter storage interfaced directly to SoC SPI master with minimal glue logic.

Use Value: 5 MHz interface speed enables <100 µs parameter load time at boot; Grade 1 temp rating supports placement near image sensor heat sources.

Electric Power Steering (EPS)

Body Control Module (BCM)

Use Scenario: Maintaining torque sensor zero-point compensation and motor phase alignment data after power-down.

IC Role / Device Role / Timing Role: Safety-critical EEPROM supporting ASIL-B requirements for steering assist functionality.

Use Value: Block protection isolates calibration data from firmware updates; HOLD pin allows MCU to service CAN interrupts without losing SPI context.

Use Scenario: Holding door lock configuration, seat position memory, and lighting dimming profiles across vehicle sleep/wake cycles.

IC Role / Device Role / Timing Role: Low-power serial storage with <10 µA standby current at 1.7V - extends battery life in always-on BCM designs.

Use Value: Dual voltage grade (1.7V–5.5V) enables direct connection to 1.8V MCU I/O rails; SOIC package simplifies PCB layout in space-constrained dash modules.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
M95128-DRMN6TP/K	128 Kbit SPI EEPROM, 5 MHz, -40°C to +125°C, but uses different STATUS register bit mapping (BP0/BP1 inverted) and lacks HOLD pin.	No suspend capability; requires firmware redesign to handle mid-transfer interrupts; BP configuration logic differs - not drop-in.	Select only if HOLD functionality is unused and STATUS register initialization code can be modified.
BR24G128FJ-WE2	128 Kbit I²C EEPROM, 1 MHz max, -40°C to +105°C, built-in write-cycle timer, no WP/HOLD pins.	I²C interface requires different MCU peripheral setup and arbitration handling; lower max speed limits high-throughput logging.	Choose for systems already using I²C infrastructure and where 1 MHz bandwidth suffices; avoid for SPI-native automotive platforms.

Compared with M95128-DRMN6TP/K and BR24G128FJ-WE2, the AT25128B-MAPDGV-E uniquely combines Grade 1 automotive qualification, HOLD pin for real-time SPI suspension, and SPI Mode 0/3 flexibility - making it the only option among the three qualified for ASIL-B EPS and ADAS subsystems requiring deterministic bus control.

Availability

AT25128B-MAPDGV-E is available at Aetrix Electronics and suitable for engine control units, ADAS domain controllers, and electric power steering modules requiring stable component supply across extended automotive product lifecycles.

Supply support for AT25128B-MAPDGV-E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontroller, analog, FPGA, and memory solutions, with core expertise in embedded control and automotive-grade semiconductor design.

The AT25128B-MAPDGV-E belongs to Microchip's automotive-qualified serial EEPROM product line, engineered specifically for functional safety-critical storage in AEC-Q100 Grade 1 environments - emphasizing data integrity, long-term reliability, and seamless integration with automotive microcontrollers.

FAQ

What is the maximum clock frequency supported by the AT25128B-MAPDGV-E?

The AT25128B-MAPDGV-E supports up to 5 MHz SPI clock frequency at VCC = 5.0V. At lower supply voltages (e.g., 2.5V), the maximum rated frequency remains 5 MHz per datasheet DS20006269B, though system-level timing margins may require derating. This speed enables efficient bulk reads and page writes in automotive bootloaders and configuration managers.

Does the AT25128B-MAPDGV-E support both SPI Mode 0 and Mode 3?

Yes, the AT25128B-MAPDGV-E explicitly supports SPI Modes 0 (CPOL = 0, CPHA = 0) and 3 (CPOL = 1, CPHA = 1). Both modes use rising-edge input sampling on SI and falling-edge output latching on SO. The device requires matching SCK idle state before and after CS assertion - confirmed in Section 5.1 of the official datasheet.

How does the Write-Protect (WP) pin function on the AT25128B-MAPDGV-E?

The WP pin on the AT25128B-MAPDGV-E inhibits all STATUS register writes when WPEN = 1 and WP is driven low. When WPEN = 0, WP has no effect - allowing STATUS register updates even with WP tied to GND. This dual-mode behavior enables flexible system-level protection schemes without requiring firmware changes during hardware integration.

What is the endurance and data retention specification for the AT25128B-MAPDGV-E?

The AT25128B-MAPDGV-E guarantees 1,000,000 write cycles and 100 years of data retention at 55°C, as validated per AEC-Q100 qualification testing. These figures are measured under specified conditions (VCC = 5.0V, TA = 25°C for endurance; TA = 55°C for retention) and reflect actual cell-level performance, not extrapolated projections.

Is the AT25128B-MAPDGV-E pin-compatible with other members of the AT25128B family?

Yes, the AT25128B-MAPDGV-E shares identical 8-lead SOIC pinout and electrical characteristics with all AT25128B variants (e.g., AT25128B-MAHD-T, AT25128B-XMD-T). Pin functions (CS, SO, WP, GND, SI, SCK, HOLD, VCC), timing parameters, and command set are fully consistent across the family - enabling direct substitution within the same package type.

AT25128B-MAPDGV-E Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 8-UFDFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 128Kbit

Memory Organization:: 16K x 8

Memory Interface:: SPI

Clock Frequency:: 5 MHz

Write Cycle Time - Word, Page:: 5ms

Access Time:: -

Voltage - Supply:: 2.5V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: 8-UDFN (2x3)

AT25128B-MAPDGV-E FAQ

1.How can I place an order for AT25128B-MAPDGV-E through Aetrix?

Please submit a Request for Quotation (RFQ) for AT25128B-MAPDGV-E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT25128B-MAPDGV-E reliable?

The price and inventory of AT25128B-MAPDGV-E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25128B-MAPDGV-E is usually 5 days.

3.What payment methods are accepted for AT25128B-MAPDGV-E?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25128B-MAPDGV-E transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT25128B-MAPDGV-E?

AT25128B-MAPDGV-E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT25128B-MAPDGV-E order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT25128B-MAPDGV-E?

For technical support, including AT25128B-MAPDGV-E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25128B-MAPDGV-E requirements.

6.How does Aetrix verify that AT25128B-MAPDGV-E is sourced from the original manufacturer or authorized distributors?

All AT25128B-MAPDGV-E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25128B-MAPDGV-E meets industry standards.

7.What is the process for return or replacement of AT25128B-MAPDGV-E?

All AT25128B-MAPDGV-E units undergo pre-shipment inspection (PSI). If there is an issue with AT25128B-MAPDGV-E, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT25128B-MAPDGV-E part is unused and in its original packaging.

Return procedure for AT25128B-MAPDGV-E:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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