Microchip Technology AT25128B-MAPDGV-T

Overview

AT25128B-MAPDGV-T from Microchip Technology is an AEC-Q100 Grade 1 automotive-qualified SPI serial EEPROM with 128 Kbits (16,384 × 8) organization, 5 MHz max clock rate at 5V, 64-byte page write capability, and -40°C to +125°C operating range. It integrates hardware write protection via WP pin, HOLD suspend functionality, and block-level array protection (1/4, 1/2, or full). Used for calibration data storage in engine control units and ADAS sensor modules.

For engineers reviewing the AT25128B-MAPDGV-T datasheet, AT25128B-MAPDGV-T pinout, AT25128B-MAPDGV-T application, or AT25128B-MAPDGV-T equivalent, key selection criteria include Grade 1 temperature compliance, SPI Mode 0/3 compatibility, 1,000,000 write endurance, 100-year data retention, and dual-voltage operation (1.7V–5.5V).

Technical Context

The AT25128B-MAPDGV-T implements a synchronous SPI slave interface with fixed MSb-first data framing, rising-edge input sampling on SI, and falling-edge output latching on SO. Its internal architecture includes a nonvolatile STATUS register controlling WPEN, BP1/BP0 block protection bits, WEL latch, and RDY/BSY flag.

It supports two SPI modes-Mode 0 (SCK idle low) and Mode 3 (SCK idle high)-with identical timing for data capture and output edges. The HOLD pin enables mid-sequence suspension without resetting SCK, while the WP pin provides hardware-enforced write inhibition when WPEN=1 and WP=low.

Key Specifications

Pinout & Package

AT25128B-MAPDGV-T is packaged in an 8-lead SOIC (Small Outline Integrated Circuit) with standard JEDEC MS-012AC footprint, 1.27 mm pitch, and RoHS-compliant lead-free finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with M95128-DFMN6TP and BR24G128FJ-3GE2, the AT25128B-MAPDGV-T uniquely delivers full AEC-Q100 Grade 1 qualification, integrated HOLD functionality, and factory-default WPEN=0 enabling flexible write-protection deployment without board-level redesign.

Availability

AT25128B-MAPDGV-T is available at Aetrix Electronics and suitable for engine control units, ADAS sensor modules, and body control modules requiring stable component supply across automotive production lifecycles.

Supply support for AT25128B-MAPDGV-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, with broad automotive qualification expertise and ISO/TS 16949-certified manufacturing.

The AT25128B-MAPDGV-T belongs to Microchip's automotive-grade serial EEPROM product line, engineered specifically for reliable nonvolatile data storage in harsh-temperature, safety-conscious vehicle subsystems.

FAQ

What is the operating temperature range certified for the AT25128B-MAPDGV-T?

The AT25128B-MAPDGV-T is AEC-Q100 qualified to Grade 1, with a certified operating temperature range of -40°C to +125°C. This specification is validated per automotive stress test standards and applies to the full 128 Kbit memory array, STATUS register, and all I/O functionality-not just DC characteristics. The AT25128B-MAPDGV-T maintains full timing compliance and write endurance across this range.

Does the AT25128B-MAPDGV-T support both SPI Mode 0 and Mode 3, and how does it affect system integration?

Yes, the AT25128B-MAPDGV-T supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In both modes, data is sampled on the rising edge of SCK and output on the falling edge-only the idle state of SCK differs. System integration requires matching the MCU's SPI controller mode and ensuring SCK polarity remains consistent before and after CS assertion. Mode 0 is default in most reference designs.

How does the HOLD pin function in the AT25128B-MAPDGV-T, and what happens if it is asserted during an active write cycle?

The HOLD pin in the AT25128B-MAPDGV-T suspends ongoing SPI communication while preserving internal address and command state-but it has no effect on an active internal write cycle. If asserted during a write, the AT25128B-MAPDGV-T continues programming the EEPROM array to completion. HOLD only affects serial data transfer; it does not interrupt or abort self-timed write operations, which remain fully autonomous once initiated.

What write protection mechanisms are implemented in the AT25128B-MAPDGV-T, and how do they interact?

The AT25128B-MAPDGV-T implements three-tiered write protection: (1) WP pin hardware lock (active low when WPEN=1), (2) STATUS register BP1/BP0 bits for 1/4, 1/2, or full array block protection, and (3) WREN instruction requirement to set WEL before any write. These layers operate independently-WP can override software writes, while BP bits restrict address ranges regardless of WP state. All are retained across power cycles.

Is the AT25128B-MAPDGV-T pin-compatible with other members of the AT25128B/AT25256B family, and what are the key distinctions?

Yes, the AT25128B-MAPDGV-T shares identical pinout, package (8-lead SOIC), and SPI command set with all AT25128B variants-including AT25128B-MAHD-T and AT25128B-XMD-T. Key distinctions lie in temperature grade (Grade 1 vs. Grade 3), packaging (SOIC vs. TSSOP/UDFN), and marking. The "MAPDGV-T" suffix denotes Grade 1 qualification, Pb-free SOIC, and tape-and-reel packaging-critical for automotive traceability and thermal compliance.