My Inquiry
My Account
Microchip Technology AT25128B-SSPDGV-T
- Part No.:
- AT25128B-SSPDGV-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25128B-SSPDGV-T.pdf
- Description:
- IC EEPROM 128KBIT SPI 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,568
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25128B-SSPDGV-T from Microchip Technology is a 128 Kbit (16,384 × 8) SPI serial EEPROM optimized for automotive systems, supporting AEC-Q100 Grade 1 operation from −40°C to +125°C, 2.5V–5.5V supply, and 5 MHz clock rate at 5V. It features hardware write protection via WP pin, HOLD suspend functionality, and 64-byte page write capability.
For engineers reviewing the AT25128B-SSPDGV-T datasheet, AT25128B-SSPDGV-T pinout, AT25128B-SSPDGV-T application, or AT25128B-SSPDGV-T equivalent, key selection criteria include automotive temperature compliance, SPI Mode 0/3 compatibility, block-level write protection granularity (1/4, 1/2, or full array), and 1M write-cycle endurance with 100-year data retention.
Technical Context
The AT25128B-SSPDGV-T implements a synchronous SPI slave interface with fixed MSb-first data framing, rising-edge input sampling on SI, and falling-edge output latching on SO. Its internal architecture includes a nonvolatile STATUS register controlling WPEN, BP1/BP0, WEL, and RDY/BSY bits, enabling flexible software/hardware write protection and status polling.
It supports dual-voltage-grade operation: Grade 1 (2.5V–5.5V, −40°C to +125°C) and Grade 3 (1.7V–5.5V, −40°C to +85°C). The device integrates Power-on Reset (POR), automatic self-timed write cycles ≤5 ms, and high-impedance SO during CS deassertion or HOLD activation - critical for multi-device SPI bus sharing in safety-critical ECUs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbits (16,384 × 8), organized as byte-addressable EEPROM array |
| Interface | SPI-compatible slave; supports Modes 0 (CPOL=0, CPHA=0) and 3 (CPOL=1, CPHA=1) |
| Max Clock Rate | 5 MHz at VCC = 5.0V; enables fast firmware parameter updates in real-time control loops |
| Write Endurance | 1,000,000 cycles per memory location - sufficient for logging, calibration, and configuration storage in 15+ year vehicle lifetimes |
| Data Retention | 100 years at TA = 55°C - ensures long-term reliability of stored calibration data without refresh |
| Operating Temp | AEC-Q100 Grade 1: −40°C to +125°C case temperature - validated for under-hood and transmission control module use |
| Supply Voltage | 2.5V to 5.5V (Grade 1); supports direct connection to 3.3V or 5V MCU I/O rails without level shifting |
| Page Write Size | 64 bytes per page write - reduces write latency vs. byte-write; enables efficient bulk parameter storage |
Pinout & Package
AT25128B-SSPDGV-T is supplied in an 8-lead SOIC package (3.9 mm × 4.9 mm, 1.27 mm pitch), RoHS-compliant and halide-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable; must be low before SCK edge to initiate command; requires pull-up resistor (≤10 kΩ) for robust power-up behavior |
| SO | Serial Data Output | Tri-state output; data valid on falling SCK edge; high-impedance when CS high or HOLD active |
| WP | Write-Protect | Hardware lock for STATUS register writes when WPEN=1; allows system-level protection independent of firmware state |
| GND | Ground Reference | Common return path for VCC and all I/O; must be low-impedance connection to minimize noise coupling into EEPROM reads |
| SI | Serial Data Input | Command/address/data input; sampled on rising SCK edge; MSb-first framing required |
| SCK | Serial Clock Input | Asynchronous master-generated clock; defines timing for SI sampling and SO output; idle polarity depends on SPI mode |
| HOLD | Suspend Control | Pauses ongoing SPI transfer without resetting sequence; enables time-critical MCU interrupts without corrupting EEPROM access |
| VCC | Power Supply | 2.5V–5.5V nominal; must ramp monotonically at ≤0.1 V/µs; POR circuit ensures no spurious writes during power-up |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Qualified | Grade 1 qualification ensures reliability in automotive ECU environments including engine control, ADAS sensors, and body electronics |
| Block Write Protection | Configurable via STATUS register (BP1/BP0) to protect 0%, 25%, 50%, or 100% of memory - prevents accidental overwrite of critical calibration tables |
| Hardware + Software Protection | Combines WP pin (hardware lock) and WREN/WRSR commands (software control) for layered security against unintended writes |
| Self-Timed Write Cycle | ≤5 ms maximum duration with automatic busy-flag (RDY/BSY) reporting - eliminates need for fixed delay timers in host firmware |
| Low Standby Current | 0.1 µA typical at 1.7V - minimizes quiescent power draw in always-on vehicle modules such as telematics gateways |
| Green Packaging | Lead-free, halide-free, RoHS-compliant SOIC - meets global automotive environmental compliance requirements (e.g., ELV, REACH) |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
|
Use Scenario: Storing adaptive fuel trim values, misfire counters, and diagnostic trouble codes (DTCs) across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with guaranteed write integrity during voltage transients and rapid power-down events. Use Value: Enables closed-loop engine optimization over vehicle lifetime while meeting ISO 16750-2 electrical stress requirements. |
Use Scenario: Retaining camera calibration offsets, radar fusion parameters, and sensor alignment data after system reset. IC Role / Device Role / Timing Role: High-reliability configuration memory that survives thermal cycling and vibration in front-end sensor modules. Use Value: Maintains ADAS accuracy without requiring re-calibration after every power cycle or firmware update. |
| Transmission Control Module (TCM) | Body Control Module (BCM) |
|
Use Scenario: Logging gear shift history, clutch wear metrics, and torque converter lock-up profiles for predictive maintenance. IC Role / Device Role / Timing Role: Endurance-optimized EEPROM interfacing directly with 3.3V microcontroller SPI peripheral. Use Value: Supports >1 million shift cycles with deterministic write latency ≤5 ms - critical for ASIL-B functional safety compliance. |
Use Scenario: Storing user preferences (seat position, mirror angle, lighting themes) and door lock configuration across battery disconnect events. IC Role / Device Role / Timing Role: Low-power, temperature-stable nonvolatile memory accessible during wake-up from ultra-low-power sleep modes. Use Value: Delivers <1 µA standby current and 100-year data retention - eliminates need for backup capacitors or supercapacitors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95128-DRMN6TP/K | 128 Kbit SPI EEPROM, AEC-Q100 Grade 1, but rated only to +105°C (not +125°C); uses different STATUS register layout and lacks HOLD pin | Acceptable for cabin modules or infotainment where ambient temp ≤+105°C; not suitable for under-hood TCM or ECU placement | Select if +125°C operation is unnecessary and HOLD functionality is unused in target design |
| BR24G128FJ-WE2 | 128 Kbit I²C EEPROM (not SPI), AEC-Q100 Grade 1, +125°C, but slower max clock (1 MHz), no hardware WP/HOLD, and different addressing scheme | Requires I²C bus resources and firmware changes; lacks suspend capability for time-critical interrupt handling | Choose only when SPI bus is saturated and I²C is available; verify timing margins for real-time parameter updates |
Compared with M95128-DRMN6TP/K and BR24G128FJ-WE2, the AT25128B-SSPDGV-T uniquely delivers full AEC-Q100 Grade 1 compliance up to +125°C, integrated HOLD functionality for deterministic interrupt response, and hardware write protection - making it the only option qualified for high-temperature, safety-critical SPI-based automotive control nodes.
Availability
AT25128B-SSPDGV-T is available at Aetrix Electronics and suitable for engine control units, ADAS sensor modules, transmission control systems, and body electronics requiring stable component supply across extended automotive lifecycles.
Supply support for AT25128B-SSPDGV-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog devices, and memory solutions, with deep expertise in automotive-grade semiconductors and functional safety certification.
The AT25128B-SSPDGV-T belongs to Microchip's automotive-qualified serial EEPROM product line, designed specifically for reliable, low-power, high-endurance nonvolatile storage in safety-critical vehicle subsystems.
FAQ
What is the operating temperature range certified for the AT25128B-SSPDGV-T?
The AT25128B-SSPDGV-T is AEC-Q100 qualified to Grade 1, with a certified operating case temperature range of −40°C to +125°C. This rating is verified per the official Microchip DS20006269B datasheet and applies to the specific SOIC package variant denoted by the -SSPDGV-T suffix. Operation outside this range may compromise data retention or write endurance.
Does the AT25128B-SSPDGV-T support SPI Mode 3, and how is it configured?
Yes, the AT25128B-SSPDGV-T supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). No internal configuration is required - the device automatically adapts based on SCK idle polarity. In Mode 3, SCK remains high when CS is deasserted; the host MCU must maintain consistent idle polarity before and after each CS assertion to avoid communication errors.
How does the HOLD pin function during an active write cycle in the AT25128B-SSPDGV-T?
The HOLD pin has no effect on an ongoing internal write cycle in the AT25128B-SSPDGV-T. While HOLD can pause SPI command transfers (e.g., mid-READ or mid-WRITE instruction), it does not interrupt or suspend the self-timed EEPROM write operation once initiated. The RDY/BSY bit remains '1' until the write completes, regardless of HOLD state.
What is the factory default state of the STATUS register in the AT25128B-SSPDGV-T?
At shipment, the AT25128B-SSPDGV-T has WPEN = 0 (write-protection disabled), BP1/BP0 = 00 (no array protection), WEL = 0 (write latch inactive), and RDY/BSY = 0 (ready). The EEPROM array contains all 0xFFh bytes. These defaults allow immediate read/write access without prior configuration - critical for first-boot calibration routines.
Can the AT25128B-SSPDGV-T be used in 1.8V systems, and what are the limitations?
Yes - the AT25128B-SSPDGV-T supports 1.7V to 5.5V operation (Grade 3), so it functions reliably at 1.8V. However, at 1.8V, the maximum SCK frequency drops to ≤1 MHz (per AC characteristics table), and VOL/VOL2 specifications apply (VOL2 ≤0.2V at IOL = 0.15 mA). System designs must verify timing margins and logic thresholds at 1.8V.
AT25128B-SSPDGV-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 5 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25128B-SSPDGV-T FAQ
1.How can I place an order for AT25128B-SSPDGV-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25128B-SSPDGV-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25128B-SSPDGV-T reliable?
The price and inventory of AT25128B-SSPDGV-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25128B-SSPDGV-T is usually 5 days.
3.What payment methods are accepted for AT25128B-SSPDGV-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25128B-SSPDGV-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25128B-SSPDGV-T?
AT25128B-SSPDGV-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25128B-SSPDGV-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25128B-SSPDGV-T?
For technical support, including AT25128B-SSPDGV-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25128B-SSPDGV-T requirements.
6.How does Aetrix verify that AT25128B-SSPDGV-T is sourced from the original manufacturer or authorized distributors?
All AT25128B-SSPDGV-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25128B-SSPDGV-T meets industry standards.
7.What is the process for return or replacement of AT25128B-SSPDGV-T?
All AT25128B-SSPDGV-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25128B-SSPDGV-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25128B-SSPDGV-T part is unused and in its original packaging.
Return procedure for AT25128B-SSPDGV-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25128B-SSPDGV-T Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
