Microchip Technology AT25160BN-SH-T
- Part No.:
- AT25160BN-SH-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25160BN-SH-T.pdf
- Description:
- IC EEPROM 16KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,227
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Product details
Overview
AT25160BN-SH-T from Microchip Technology (formerly Atmel) is a 16-kbit SPI serial EEPROM organized as 2048 × 8-bit memory, operating from 1.8 V to 5.5 V, supporting 20 MHz clock rate at 5 V, featuring 32-byte page write and hardware/software write protection. It serves as nonvolatile configuration storage in industrial controllers, sensor nodes, and power management ICs where low-voltage operation and data retention are critical.
For engineers reviewing the AT25160BN-SH-T datasheet, AT25160BN-SH-T pinout, AT25160BN-SH-T application, or AT25160BN-SH-T equivalent, key selection criteria include its 1.8–5.5 V supply range, 20 MHz max SPI clock (5 V), 32-byte page write capability, block write protection granularity (1/4, 1/2, or full array), and JEDEC SOIC-8 package with NiPdAu lead finish.
Technical Context
The AT25160BN-SH-T implements a synchronous SPI slave interface compliant with Modes 0 and 3, using separate SI (input) and SO (output) pins for full-duplex communication. Its internal architecture includes an 8-bit instruction register, status register with RDY/BUSY flag and BP0/BP1 protection bits, and nonvolatile control cells for write protection settings.
It supports self-timed internal write cycles (≤5 ms), requires explicit WREN before WRITE/WRSR instructions, and uses CS-driven selection with HOLD pin for serial communication suspension without reset. Block protection is configured via WRSR and enforced during both software writes and hardware WP pin assertion when WPEN=1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 16 kbit (2048 × 8-bit words) - provides sufficient space for firmware parameters, calibration data, or device identity storage in compact embedded systems. |
| Supply Voltage Range | 1.8 V to 5.5 V - enables direct interfacing with 1.8 V, 3.3 V, and 5 V microcontrollers without level shifting. |
| Max SPI Clock Frequency | 20 MHz at VCC = 5.0 V - supports high-speed configuration reads/writes in time-critical boot or runtime update sequences. |
| Page Write Size | 32 bytes - minimizes write latency per transaction and reduces wear on individual pages compared to byte-write-only devices. |
| Write Endurance | 1 million cycles - ensures reliable field updates over product lifetime in applications requiring frequent parameter logging or calibration adjustment. |
| Data Retention | 100 years - guarantees long-term integrity of stored configuration or security keys without refresh. |
| Operating Temperature | −40°C to +85°C - qualified for industrial environments including motor drives, PLC I/O modules, and outdoor sensing equipment. |
Pinout & Package
AT25160BN-SH-T is packaged in an 8-lead JEDEC SOIC (package code 8S1), 3.9 mm × 4.9 mm body, 1.27 mm pitch, NiPdAu lead finish. Pinout follows standard SOIC-8 orientation with Pin 1 marked by notch or dot.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select input | Active-low enable: asserts SPI slave mode; falling edge initiates instruction sequence; must remain low during full command frame. |
| SCK | Serial Clock input | Master-generated clock synchronizing all SI/SO data transfers; supports Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). |
| SI | Serial Data Input | Receives opcodes, addresses, and write data MSB-first; ignored during HOLD or when CS is high. |
| SO | Serial Data Output | Drives read data MSB-first; enters high-impedance state when CS is high or during internal write cycle. |
| GND | Ground reference | Primary return path for VCC current and signal references; must be low-impedance to minimize noise coupling into SPI lines. |
| VCC | Power supply | Single-supply input (1.8–5.5 V); decoupling capacitor (0.1 µF) required within 10 mm of pin for stable operation. |
| WP | Write Protect input | Hardware lock: when WPEN=1 and WP=low, blocks all status register writes and protected memory writes. |
| HOLD | Communication suspend | Pauses ongoing SPI transfer (e.g., mid-read) without resetting sequence; requires SCK low during assertion/deassertion. |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Configurable via status register to protect 1/4, 1/2, or entire 2048-word array - prevents accidental overwrite of critical bootloader or calibration sectors. |
| Hardware + Software Write Protection | WP pin (hardware) and WREN/WRDI instructions (software) provide layered defense against unintended writes during power transitions or firmware faults. |
| Self-timed Write Cycle | No external erase step required; internal timing completes write in ≤5 ms - simplifies host firmware and eliminates need for polling delay loops. |
| Industrial Temperature Range | −40°C to +85°C operation - validated for use in factory automation, energy metering, and automotive under-hood auxiliary modules. |
| Low Standby Current | ≤6.0 µA at 1.8 V (ISB1) - extends battery life in portable or energy-harvesting sensor nodes during extended sleep periods. |
Applications
| Industrial PLC Configuration Storage | Smart Sensor Calibration Memory |
|---|---|
Use Scenario: Storing I/O mapping tables, scaling coefficients, and alarm thresholds in programmable logic controller modules. IC Role / Device Role / Timing Role: Nonvolatile configuration EEPROM interfaced directly to ARM Cortex-M4 host MCU via SPI bus. Use Value: Enables field-upgradable parameter sets without firmware reflash; 1.8–5.5 V operation matches wide-input industrial power rails. | Use Scenario: Retaining factory-calibrated offset/gain values and temperature compensation curves in MEMS pressure sensors. IC Role / Device Role / Timing Role: SPI-connected persistent memory holding sensor-specific trim data accessed at power-on reset. Use Value: 100-year data retention ensures calibration integrity across product lifecycle; 32-byte page write accelerates multi-parameter updates. |
| Power Supply Sequencing Controller | Medical Device Usage Log |
Use Scenario: Storing startup delay timers, voltage ramp rates, and fault recovery policies in multi-rail DC-DC sequencers. IC Role / Device Role / Timing Role: Configuration EEPROM co-located with PMIC, accessed during power-up initialization sequence. Use Value: Block write protection prevents corruption of safety-critical sequencing parameters during brownout conditions. | Use Scenario: Recording operational hours, error codes, and maintenance intervals in portable diagnostic equipment. IC Role / Device Role / Timing Role: Low-power SPI EEPROM logging timestamped events to support regulatory traceability requirements. Use Value: ≤6.0 µA standby current extends battery runtime between log entries; 1 million endurance supports daily logging for >27 years. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95160-WMN6TP | STMicroelectronics 16-kbit SPI EEPROM; identical 1.8–5.5 V range, 20 MHz max clock, SOIC-8 package, but uses different status register bit layout and lacks HOLD pin. | Supports same industrial temperature range and page write size, but absence of HOLD limits use in systems requiring interruptible SPI transfers. | Select when HOLD functionality is unused and ST's qualification documentation aligns with program requirements. |
| BR24G16NUX-10 | Rohm 16-kbit SPI EEPROM; 1.7–5.5 V range, 10 MHz max clock (VCC ≥ 2.5 V), TSSOP-8 package, integrated write protection via WP pin only (no status register BP bits). | Limited to lower SPI speed and offers only full-array hardware protection - insufficient for partial-sector locking in complex configuration schemes. | Choose for cost-sensitive designs where 10 MHz bandwidth suffices and block-level protection is unnecessary. |
Compared with M95160-WMN6TP and BR24G16NUX-10, the AT25160BN-SH-T uniquely combines HOLD pin support, configurable block protection (BP0/BP1), and 20 MHz operation at 5 V - making it optimal for real-time industrial systems requiring robust, interruptible, and granular nonvolatile storage.
Availability
AT25160BN-SH-T is available at Aetrix Electronics and suitable for industrial PLCs, smart sensors, power sequencers, and medical logging devices requiring stable component supply across extended production lifecycles.
Supply support for AT25160BN-SH-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog components, and memory solutions, with broad industrial and automotive qualification capabilities.
The AT25160BN-SH-T belongs to Microchip's legacy Atmel serial EEPROM product line, designed specifically for reliable, low-voltage, SPI-based nonvolatile storage in space-constrained industrial and commercial systems.
FAQ
What is the maximum SPI clock frequency supported by the AT25160BN-SH-T?
The AT25160BN-SH-T supports up to 20 MHz SPI clock frequency when operated at VCC = 5.0 V. At lower supply voltages (e.g., 1.8 V or 2.7 V), the maximum rated clock drops to 5 MHz and 10 MHz respectively, as specified in Table 0-4 of the datasheet. This voltage-dependent timing ensures reliable signal integrity across its full 1.8–5.5 V operating range.
Does the AT25160BN-SH-T require an external erase command before writing?
No, the AT25160BN-SH-T does not require a separate erase command. All write operations are self-timed and internally managed; the device automatically erases the target page before programming new data. A Write Enable (WREN) instruction must precede any WRITE or WRSR command, and the internal write cycle completes in ≤5 ms without host intervention.
How is write protection implemented on the AT25160BN-SH-T?
The AT25160BN-SH-T implements dual-layer write protection: software-based via status register bits BP0/BP1 (configurable 1/4, 1/2, or full array lock) and hardware-based via the WP pin when WPEN=1. When WP is low and WPEN=1, writes to protected memory and the status register are blocked - providing fail-safe defense against accidental or malicious modification.
What package type and lead finish does the AT25160BN-SH-T use?
The AT25160BN-SH-T uses an 8-lead JEDEC SOIC package (package code 8S1) with NiPdAu lead finish. This RoHS-compliant, lead-free finish ensures solderability and corrosion resistance in automated assembly processes, and the SOIC-8 footprint is compatible with standard PCB layouts used for legacy and modern serial EEPROMs.
Can the AT25160BN-SH-T operate reliably at 1.8 V supply?
Yes, the AT25160BN-SH-T is fully specified for operation at 1.8 V, with guaranteed performance across −40°C to +85°C. At 1.8 V, it supports SPI clock frequencies up to 5 MHz, maintains ≤6.0 µA standby current (ISB1), and delivers full 1 million write cycles and 100-year data retention - making it suitable for battery-powered and ultra-low-power embedded systems.
AT25160BN-SH-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 16Kbit
- Memory Organization:
- 2K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25160BN-SH-T FAQ
1.How can I place an order for AT25160BN-SH-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25160BN-SH-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25160BN-SH-T reliable?
The price and inventory of AT25160BN-SH-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25160BN-SH-T is usually 5 days.
3.What payment methods are accepted for AT25160BN-SH-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25160BN-SH-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25160BN-SH-T?
AT25160BN-SH-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25160BN-SH-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25160BN-SH-T?
For technical support, including AT25160BN-SH-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25160BN-SH-T requirements.
6.How does Aetrix verify that AT25160BN-SH-T is sourced from the original manufacturer or authorized distributors?
All AT25160BN-SH-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25160BN-SH-T meets industry standards.
7.What is the process for return or replacement of AT25160BN-SH-T?
All AT25160BN-SH-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25160BN-SH-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25160BN-SH-T part is unused and in its original packaging.
Return procedure for AT25160BN-SH-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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