Microchip Technology AT25256AN-10SU-1.8
- Part No.:
- AT25256AN-10SU-1.8
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25256AN-10SU-1.8.pdf
- Description:
- IC EEPROM 256KBIT SPI 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,526
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25256AN-10SU-1.8 from Microchip Technology (formerly Atmel) is a 256 Kbit SPI serial EEPROM organized as 32,768 × 8 bits, operating from 1.8 V to 5.5 V, supporting 20 MHz clock rate at 5 V, featuring 64-byte page write, block write protection (1/4, 1/2, or full array), and industrial temperature range (−40°C to +85°C). It serves as nonvolatile data storage in microcontroller-based embedded systems requiring low-voltage operation and robust data retention.
For engineers reviewing the AT25256AN-10SU-1.8 datasheet, AT25256AN-10SU-1.8 pinout, AT25256AN-10SU-1.8 application, or AT25256AN-10SU-1.8 equivalent, key selection criteria include 1.8 V minimum supply voltage compatibility, SOIC-8 (8S1) package footprint, SPI Mode 0/3 interface timing, 5 ms max self-timed write cycle, and hardware/software write protection via WP/HOLD pins.
Technical Context
The AT25256AN-10SU-1.8 implements a synchronous SPI slave interface with separate SI (input) and SO (output) lines, CS-controlled selection, and MSB-first data transfer. It uses an 8-bit instruction register with op-codes for WREN, WRITE, READ, RDSR, WRSR, and WRDI - all requiring CS low-to-high transition to initiate internal operations.
Its memory architecture supports byte and page writes, automatic address incrementing within 64-byte boundaries, and nonvolatile status register bits (BP0/BP1/WPEN) that control block protection and hardware write enable. The HOLD pin suspends ongoing serial communication without resetting the sequence, while WP enables hardware lock of protected regions when WPEN = 1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 256 Kbit (32,768 × 8 bits) - provides sufficient nonvolatile storage for firmware parameters, calibration data, or configuration registers in space-constrained designs. |
| Supply Voltage Range | 1.8 V to 5.5 V - enables direct interfacing with 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level-shifting. |
| Max Clock Frequency | 20 MHz at VCC = 5.0 V - supports high-speed read/write bursts in real-time embedded applications. |
| Write Cycle Time | 5 ms maximum - defines worst-case latency for persistent data commits; impacts system responsiveness during configuration updates. |
| Endurance & Retention | 1 million write cycles / >100 years data retention - ensures long-term reliability in field-deployed industrial controllers and metering devices. |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade operation without derating in harsh ambient environments. |
| Interface Protocol | SPI Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 1) - compatible with broad MCU families including ARM Cortex-M, PIC, and AVR. |
Pinout & Package
AT25256AN-10SU-1.8 is packaged in an 8-lead JEDEC SOIC (8S1), 0.150" wide body, RoHS-compliant and lead-free/halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be low to accept instructions and data; high impedance on SO when CS is high. |
| SCK | Serial Clock | Input clock synchronizing all data transfers; determines maximum interface speed and timing margins. |
| SI | Serial Data Input | Receives op-codes, addresses, and write data; sampled on SCK edge per SPI mode. |
| SO | Serial Data Output | Drives read data and status bits; tri-states when CS is high or HOLD is asserted. |
| GND | Ground Reference | Return path for VCC and all I/O signals; requires low-impedance PCB connection to minimize noise coupling. |
| VCC | Power Supply | Single supply input (1.8–5.5 V); powers core logic and I/O buffers; bypass capacitor required near pin. |
| WP | Write Protect | Hardware lock for status register and protected memory blocks when WPEN = 1; prevents accidental writes during power transitions. |
| HOLD | Communication Suspend | Pauses active SPI transaction without resetting state machine; allows host CPU to service higher-priority interrupts. |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte Page Write | Reduces total programming time by up to 64× vs. byte writes; minimizes host MCU overhead during bulk data storage. |
| Block Write Protection | Configurable via status register (BP0/BP1) to lock top 1/4, 1/2, or entire memory array - secures boot code or factory calibration data. |
| Hardware + Software Write Protection | WP pin + WRSR instruction allow layered security: physical lock (WP low + WPEN=1) and logical lock (BP bits set). |
| Self-timed Internal Write Cycle | Eliminates need for external timing control or polling delay loops; RDSR instruction confirms completion via RDY bit. |
| Industrial Temperature Range | Validated operation from −40°C to +85°C ensures reliability in motor drives, PLCs, and outdoor IoT gateways. |
Applications
| Smart Energy Metering | Industrial PLC Configuration Storage |
|---|---|
Use Scenario: Storing tariff tables, meter calibration constants, and tamper-event logs in DIN-rail mounted electricity meters. IC Role / Device Role / Timing Role: Nonvolatile parameter store interfaced directly to an ARM Cortex-M3 MCU via SPI at 10 MHz. Use Value: 1.8 V operation enables direct connection to meter's 2.5 V analog front-end supply; 1M endurance supports daily log writes over 10+ years. |
Use Scenario: Holding ladder logic configuration, I/O mapping, and firmware update staging data in programmable logic controllers. IC Role / Device Role / Timing Role: Persistent configuration memory accessed during cold start and runtime reconfiguration. Use Value: Block protection prevents corruption of critical startup parameters; HOLD pin allows safe interruption during scan-cycle execution. |
| Medical Diagnostic Device Calibration | Automotive Body Control Module (BCM) |
Use Scenario: Storing sensor offset/gain coefficients and user-defined test protocols in portable ultrasound or ECG analyzers. IC Role / Device Role / Timing Role: Secure, low-power EEPROM co-located with ADC and microcontroller on compact diagnostic PCB. Use Value: >100-year data retention guarantees calibration integrity across device lifetime; WP pin hardens against ESD-induced writes during servicing. |
Use Scenario: Saving seat position presets, mirror settings, and lighting profiles in automotive BCMs with CAN/LIN connectivity. IC Role / Device Role / Timing Role: Secondary nonvolatile memory backing up volatile RAM contents during ignition-off periods. Use Value: SOIC-8 package fits tight under-hood layouts; 5 ms write time enables fast save-on-exit without delaying vehicle shutdown sequence. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95256-DRMN6TP/K | STMicroelectronics 256 Kbit SPI EEPROM; 1.8–5.5 V; 20 MHz max; SOIC-8; same pinout but different HOLD/HP functionality (no HOLD pin - uses dedicated HP pin for hardware protection). | Lacks HOLD pin suspension capability; uses HP instead of WP for hardware lock; status register BP bits differ in encoding. | Select when HOLD functionality is unused and HP-based protection suffices; verify timing compliance with host MCU SPI controller. |
| BR25H256FJ-WE2 | Rohm 256 Kbit SPI EEPROM; 1.7–5.5 V; 10 MHz max; TSSOP-8; includes built-in error correction (ECC) and enhanced write protection with lock-bit freeze. | Lower max clock rate limits throughput; ECC improves data integrity in noisy automotive environments; TSSOP-8 requires layout change from SOIC-8. | Prefer for safety-critical automotive applications where data integrity outweighs speed; requires PCB redesign due to TSSOP footprint. |
Compared with M95256-DRMN6TP/K and BR25H256FJ-WE2, AT25256AN-10SU-1.8 offers identical SOIC-8 pin compatibility and HOLD functionality absent in the ST part, while providing higher speed than the Rohm part - making it optimal for industrial systems needing both suspend capability and 20 MHz burst reads.
Availability
AT25256AN-10SU-1.8 is available at Aetrix Electronics and suitable for smart energy metering, industrial PLC configuration storage, medical diagnostic device calibration, and automotive body control module applications requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for AT25256AN-10SU-1.8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and continues to manufacture, support, and qualify legacy Atmel serial EEPROM products including the AT25xxx family.
The AT25256A series was designed for reliable, low-voltage nonvolatile storage in industrial and commercial embedded systems - emphasizing interoperability with standard SPI controllers, robust write protection, and extended data retention under thermal stress.
FAQ
What is the supply voltage range supported by the AT25256AN-10SU-1.8?
The AT25256AN-10SU-1.8 operates from 1.8 V to 5.5 V, enabling direct integration into 1.8 V, 2.5 V, 3.3 V, and 5 V systems without level shifters. This dual-voltage capability is confirmed in Table 1-2 of the datasheet (VCC1 min = 1.8 V), and the "−1.8" suffix explicitly denotes the 1.8 V–5.5 V version. AT25256AN-10SU-1.8 maintains full AC/DC specifications across this range, including 20 MHz operation at 5 V and 5 ms write cycle at all voltages.
Does the AT25256AN-10SU-1.8 support SPI Mode 3 in addition to Mode 0?
Yes, the AT25256AN-10SU-1.8 supports both SPI Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 1), as stated in the Features section of the datasheet. This dual-mode compatibility allows seamless interfacing with diverse microcontrollers - for example, Freescale/NXP Kinetis (Mode 3 default) and STM32 (Mode 0 default) - without hardware modification. AT25256AN-10SU-1.8 does not auto-detect mode; the host must configure its SPI peripheral accordingly before issuing commands.
How does the HOLD pin function during an active SPI transaction on the AT25256AN-10SU-1.8?
The HOLD pin on the AT25256AN-10SU-1.8 suspends serial communication without resetting the internal state machine: when asserted low while SCK is low, it halts data transfer and places SO in high-impedance, allowing the host MCU to service interrupts or perform other tasks. Resuming requires bringing HOLD high while SCK remains low. This behavior is defined in Section 2 and Figure 4-8 of the datasheet. AT25256AN-10SU-1.8 retains all address and instruction context during HOLD, ensuring deterministic resumption.
What memory protection options are available on the AT25256AN-10SU-1.8?
The AT25256AN-10SU-1.8 provides three-tiered write protection: software-controlled via WRSR instruction (BP0/BP1 bits), hardware-enforced via WP pin (when WPEN = 1), and combined modes. Table 3-4 specifies protection levels - 0x00 (none), 0x01 (top 1/4: 0x6000–0x7FFF), 0x10 (top 1/2: 0x4000–0x7FFF), or 0x11 (full array: 0x0000–0x7FFF). AT25256AN-10SU-1.8 also supports write-disable instruction (WRDI) independent of WP state, adding defense-in-depth against firmware bugs.
Is the AT25256AN-10SU-1.8 pin-compatible with other packages in the AT25256A family?
No - the AT25256AN-10SU-1.8 uses the 8S1 (JEDEC SOIC) package, which has different mechanical dimensions and lead pitch than PDIP (8P3), TSSOP (8A2), dBGA2 (8U2-1), or SAP (8Y7) variants. While all share identical pin functions and electrical behavior, the 8S1 footprint (0.150" body width, 1.27 mm pitch) is not interchangeable with 8A2 (0.65 mm pitch) or 8U2-1 (0.75 mm ball pitch). AT25256AN-10SU-1.8 is only pin- and footprint-compatible with other AT25256A-10SU-x parts in SOIC-8.
AT25256AN-10SU-1.8 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25256AN-10SU-1.8 FAQ
1.How can I place an order for AT25256AN-10SU-1.8 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25256AN-10SU-1.8 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25256AN-10SU-1.8 reliable?
The price and inventory of AT25256AN-10SU-1.8 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25256AN-10SU-1.8 is usually 5 days.
3.What payment methods are accepted for AT25256AN-10SU-1.8?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25256AN-10SU-1.8 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25256AN-10SU-1.8?
AT25256AN-10SU-1.8 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25256AN-10SU-1.8 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25256AN-10SU-1.8?
For technical support, including AT25256AN-10SU-1.8 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25256AN-10SU-1.8 requirements.
6.How does Aetrix verify that AT25256AN-10SU-1.8 is sourced from the original manufacturer or authorized distributors?
All AT25256AN-10SU-1.8 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25256AN-10SU-1.8 meets industry standards.
7.What is the process for return or replacement of AT25256AN-10SU-1.8?
All AT25256AN-10SU-1.8 units undergo pre-shipment inspection (PSI). If there is an issue with AT25256AN-10SU-1.8, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25256AN-10SU-1.8 part is unused and in its original packaging.
Return procedure for AT25256AN-10SU-1.8:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25256AN-10SU-1.8 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
