Microchip Technology AT25320A-10PU-1.8
- Part No.:
- AT25320A-10PU-1.8
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT25320A-10PU-1.8.pdf
- Description:
- IC EEPROM 32KBIT SPI 20MHZ 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,025
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Product details
Overview
AT25320A-10PU-1.8 from Microchip Technology (formerly Atmel) is a 32-Kbit SPI serial EEPROM organized as 4096 × 8 bits, operating from 1.8 V to 5.5 V, supporting 20 MHz clock rate at 5 V, with 32-byte page write capability and hardware/software write protection. It serves as nonvolatile configuration storage in industrial controllers, sensor nodes, and power management ICs requiring low-voltage operation.
For engineers reviewing the AT25320A-10PU-1.8 datasheet, AT25320A-10PU-1.8 pinout, AT25320A-10PU-1.8 application, or AT25320A-10PU-1.8 equivalent, key selection criteria include 1.8 V minimum supply, SPI Mode 0/3 compatibility, block write protection granularity, self-timed 5 ms write cycle, and JEDEC SOIC-8 packaging with RoHS compliance.
Technical Context
The AT25320A-10PU-1.8 implements a synchronous serial peripheral interface (SPI) slave architecture with separate SI/SO lines, CS-controlled selection, and HOLD pin for communication suspension without sequence reset. It uses an 8-bit instruction register with MSB-first transmission and supports WREN/WRDI/RDSR/WRSR/READ/WRITE op-codes.
Its memory array is partitioned into four segments for block protection (none, 1/4, 1/2, or full), controlled by nonvolatile BP0/BP1 bits in the status register. Write protection combines hardware (WP pin) and software (WPEN bit) control, with WPEN enabling or disabling WP pin functionality based on status register configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 32 Kbit (4096 × 8), sufficient for firmware parameter tables or calibration data in space-constrained designs |
| Supply Voltage Range | 1.8 V to 5.5 V - enables direct interfacing with 1.8 V logic and legacy 3.3 V/5 V systems without level shifting |
| Max Clock Frequency | 20 MHz at VCC = 5 V - supports high-throughput configuration reads in real-time control loops |
| Page Write Size | 32 bytes - reduces write transaction overhead versus byte-wise programming; prevents address rollover within page boundary |
| Write Cycle Time | 5 ms max - defines minimum interval between write commands; enables deterministic timing in time-critical firmware updates |
| Endurance & Retention | 1 million write cycles / 100 years data retention - meets long-life requirements for industrial metering and automotive subsystems |
| Operating Temperature | –40°C to +85°C - qualified for industrial ambient conditions without derating |
Pinout & Package
AT25320A-10PU-1.8 is supplied in an 8-lead JEDEC SOIC package (8S1), 0.150" wide body, RoHS-compliant with green molding compound.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; device ignores SI and drives SO high-Z when CS is high |
| SCK | Serial Clock | Input-only clock; synchronizes all SI/SO data transfers; supports SPI Modes 0 and 3 |
| SI | Serial Data Input | Receives op-codes, addresses, and write data; MSB-first protocol with CS falling edge initiation |
| SO | Serial Data Output | Drives read data and status register contents; tri-states when CS is high or HOLD is asserted |
| GND | Ground Reference | Return path for VCC and all I/O signals; requires low-impedance PCB connection to minimize noise coupling |
| VCC | Power Supply | Single supply input; supports 1.8–5.5 V operation; bypass capacitor recommended per datasheet layout guidelines |
| WP | Write Protect | Hardware lock for status register writes when WPEN = 1; no effect if WPEN = 0 |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer without resetting internal address counter; requires SCK low during assertion |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode 0 & 3 Support | Interoperates with microcontrollers using either clock polarity/phase configuration, reducing host-side driver complexity |
| Block Write Protection | Four protection levels (none, 1/4, 1/2, full array) configurable via nonvolatile status register bits BP0/BP1 |
| Hardware + Software Write Lock | WP pin and WRSR instruction jointly control access to protected regions and status register, enabling layered security |
| Self-Timed Write Cycle | No external timing control needed; internal circuitry manages erase/write/verify sequence within 5 ms max duration |
| Low-Voltage Operation | Full functionality down to 1.8 V enables integration into battery-powered IoT sensors and ultra-low-power MCUs |
Applications
| Industrial PLC Configuration Storage | Smart Sensor Calibration Data Retention |
|---|---|
Use Scenario: Storing I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers deployed in factory automation cabinets. IC Role / Device Role / Timing Role: Nonvolatile configuration EEPROM interfaced to ARM Cortex-M7 host MCU via SPI at 10 MHz. Use Value: Enables field-updatable parameters without firmware reflash; 100-year retention ensures data integrity across equipment lifetime. | Use Scenario: Holding temperature-compensated offset/gain coefficients for MEMS pressure sensors in HVAC monitoring units. IC Role / Device Role / Timing Role: SPI-connected calibration memory accessed during sensor power-up and periodic self-test sequences. Use Value: 1.8 V operation allows direct connection to sensor ASIC's low-voltage domain; 32-byte page writes reduce update latency during recalibration. |
| Power Supply Unit (PSU) Trim Settings | Medical Device Safety Parameter Backup |
Use Scenario: Storing digitally trimmed voltage/current setpoints and overvoltage protection thresholds in AC/DC switch-mode power supplies. IC Role / Device Role / Timing Role: SPI EEPROM used by digital controller (e.g., C2000 DSP) to load operational parameters at startup. Use Value: Block protection prevents accidental overwrite of critical safety settings; WP pin hardwired to system supervisor IC for fail-safe lock. | Use Scenario: Archiving device-specific safety limits (e.g., maximum infusion rate, temperature cutoffs) in portable infusion pumps. IC Role / Device Role / Timing Role: Isolated SPI interface to microcontroller with HOLD used during fault-handling interrupts to preserve transaction state. Use Value: 1 million write cycles support frequent recalibration logs; industrial temp range ensures reliability inside sterilized enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95320-DRMN3TP/K | 32 Kbit SPI EEPROM, 1.8–5.5 V, 20 MHz, SOIC-8, but uses different status register map and lacks HOLD pin | No HOLD functionality limits use in interrupt-driven systems requiring pause/resume; identical block protection scheme | Select when HOLD is unused and STMicroelectronics supply chain preference applies |
| BR24T32FJ-WE2 | 32 Kbit I²C EEPROM, 1.7–5.5 V, 1 MHz max, TSSOP-8, with write protect pin and 100-year retention | I²C interface requires different MCU peripheral setup and has lower bandwidth than SPI; no page write suspend capability | Choose for designs already using I²C bus infrastructure and where 20 MHz SPI speed is unnecessary |
Compared with M953220-DRMN3TP/K and BR24T32FJ-WE2, the AT25320A-10PU-1.8 uniquely provides both HOLD and WP pins in SOIC-8 with full SPI Mode 0/3 support, making it optimal for deterministic, interrupt-resilient configuration storage in resource-constrained industrial hosts.
Availability
AT25320A-10PU-1.8 is available at Aetrix Electronics and suitable for industrial PLCs, smart sensor nodes, power supply units, and medical device safety parameter backup requiring stable component supply and long-term obsolescence management.
Supply support for AT25320A-10PU-1.8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with broad industrial and automotive qualification coverage.
The AT25320A-10PU-1.8 belongs to Microchip's serial EEPROM product line, designed specifically for reliable, low-voltage nonvolatile storage in embedded systems where SPI interface simplicity and robust data integrity are critical.
FAQ
What is the minimum supply voltage required for AT25320A-10PU-1.8 to operate correctly?
The AT25320A-10PU-1.8 operates down to 1.8 V, as confirmed by its "−1.8" suffix and DC Characteristics table specifying VCC min = 1.8 V across all operating temperatures. Below this voltage, read/write functionality is not guaranteed, and the device may fail to respond to SPI commands or corrupt data during write cycles. Always maintain VCC ≥ 1.8 V with adequate decoupling per the datasheet layout recommendations.
Does AT25320A-10PU-1.8 support SPI Mode 3, and how is it configured?
Yes, AT25320A-10PU-1.8 supports SPI Mode 3 (CPOL = 1, CPHA = 1), as explicitly stated in the Features section. No configuration is required - the device automatically interprets clock polarity and phase based on incoming SCK transitions. Mode 3 operation is validated across the full 1.8–5.5 V supply range and −40°C to +85°C temperature range per AC Characteristics tables.
How does the HOLD pin function during an active AT25320A-10PU-1.8 SPI transaction?
The HOLD pin suspends serial communication while preserving the internal address counter and command state. To activate HOLD, it must be driven low while SCK is low; the SO pin enters high-impedance, and SI inputs are ignored. Resuming requires driving HOLD high while SCK remains low. This behavior is electrically verified in Figure 4-8 and enables safe interruption during MCU interrupt service routines without restarting the entire SPI sequence.
What memory protection options are available on AT25320A-10PU-1.8, and how are they enabled?
AT25320A-10PU-1.8 offers four block write protection levels (none, 1/4, 1/2, or full array) controlled by BP0/BP1 bits in the status register, set via the WRSR instruction. Hardware protection is enabled by setting WPEN = 1 and pulling WP low. Both mechanisms are nonvolatile and survive power cycles. Protection granularity is fixed per device density: for AT25320A, "1/4" protects addresses 0xC00–0xFFF (1024 bytes).
Is AT25320A-10PU-1.8 pin-compatible with other members of the AT25xxxA family, such as AT25160A-10PU-1.8?
Yes, AT25320A-10PU-1.8 shares identical pinout, package (8-lead SOIC), and electrical interface with AT25080A/160A/640A variants - all follow the same Pin Configuration table with CS/SCK/SI/SO/GND/VCC/WP/HOLD assignments. However, memory size, address width, and block protection boundaries differ; software must account for AT25320A's 4096-word addressing (A11–A0) versus AT25160A's A10–A0.
AT25320A-10PU-1.8 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 32Kbit
- Memory Organization:
- 4K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT25320A-10PU-1.8 FAQ
1.How can I place an order for AT25320A-10PU-1.8 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25320A-10PU-1.8 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25320A-10PU-1.8 reliable?
The price and inventory of AT25320A-10PU-1.8 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25320A-10PU-1.8 is usually 5 days.
3.What payment methods are accepted for AT25320A-10PU-1.8?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25320A-10PU-1.8 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25320A-10PU-1.8?
AT25320A-10PU-1.8 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25320A-10PU-1.8 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25320A-10PU-1.8?
For technical support, including AT25320A-10PU-1.8 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25320A-10PU-1.8 requirements.
6.How does Aetrix verify that AT25320A-10PU-1.8 is sourced from the original manufacturer or authorized distributors?
All AT25320A-10PU-1.8 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25320A-10PU-1.8 meets industry standards.
7.What is the process for return or replacement of AT25320A-10PU-1.8?
All AT25320A-10PU-1.8 units undergo pre-shipment inspection (PSI). If there is an issue with AT25320A-10PU-1.8, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25320A-10PU-1.8 part is unused and in its original packaging.
Return procedure for AT25320A-10PU-1.8:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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