Microchip Technology AT25320A-10PU-2.7
- Part No.:
- AT25320A-10PU-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT25320A-10PU-2.7.pdf
- Description:
- IC EEPROM 32KBIT SPI 20MHZ 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,906
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Product details
Overview
AT25320A-10PU-2.7 from Microchip Technology (formerly Atmel) is a 32-Kbit SPI serial EEPROM organized as 4096 × 8 bits, operating from 2.7V to 5.5V, supporting 20 MHz clock rate at 5V, and featuring hardware/software write protection with 1 million write cycles endurance. It serves as nonvolatile configuration storage in industrial control modules requiring low-voltage operation and robust data retention.
For engineers reviewing the AT25320A-10PU-2.7 datasheet, AT25320A-10PU-2.7 pinout, AT25320A-10PU-2.7 application, or AT25320A-10PU-2.7 equivalent, key selection factors include its 8-lead PDIP package, 32-byte page write capability, block write protection (1/4, 1/2, or full array), HOLD pin for serial communication suspension, and compatibility with SPI Modes 0 and 3.
Technical Context
The AT25320A-10PU-2.7 operates as a slave device on a three-wire SPI bus (CS, SCK, SI/SO), using MSB-first transmission and op-code–driven command execution. Its internal architecture includes an 8-bit instruction register and nonvolatile status register with BP0/BP1/ WPEN bits controlling memory protection granularity.
It implements self-timed write cycles (≤5 ms), supports dual voltage ranges (2.7–5.5V and 1.8–5.5V variants), and integrates both hardware (WP pin) and software (WRSR/WREN/WRDI) data protection mechanisms. The HOLD pin enables pause/resume of ongoing serial transfers without resetting the sequence.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 32 Kbit (4096 × 8 bits) - provides sufficient space for firmware parameters, calibration data, or device ID storage in compact embedded systems. |
| Interface | SPI-compatible, Modes 0 and 3 - ensures interoperability with common microcontrollers including 6805 and 68HC11 families without protocol translation. |
| Supply Voltage | 2.7V to 5.5V - enables direct integration into 3.3V and 5V logic domains without level-shifting circuitry. |
| Max Clock Rate | 20 MHz at VCC = 5V - supports fast configuration reads/writes, reducing boot-time latency in time-critical applications. |
| Write Endurance | 1 million cycles - guarantees long-term reliability in systems requiring frequent parameter updates, such as programmable power supplies. |
| Data Retention | 100 years - ensures persistent storage integrity across product lifecycles, including automotive and industrial deployments. |
| Page Write Size | 32 bytes - optimizes write efficiency by minimizing transaction overhead when updating contiguous configuration blocks. |
Pinout & Package
AT25320A-10PU-2.7 uses an 8-lead JEDEC PDIP package (0.300" wide body), suitable for through-hole prototyping and legacy industrial PCBs. Pin spacing is 0.100" (2.54 mm), with standard DIP footprint compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be low to accept commands and initiate SPI transactions. |
| SCK | Serial Clock | Input-only clock input; synchronizes all data transfers; requires stable edge timing per AC specs (tWH/tWL ≥20 ns @5V). |
| SI | Serial Data Input | Receives op-codes, addresses, and write data; MSB-first format; ignored during HOLD or CS high. |
| SO | Serial Data Output | Drives read data and status bits; transitions to high-impedance when CS is high or HOLD is active. |
| GND | Ground Reference | Primary return path for VCC and I/O signals; must be low-impedance to maintain noise immunity during SPI bursts. |
| VCC | Power Supply | Supplies core logic and memory array; regulated 2.7–5.5V input required; bypass capacitor recommended near pin. |
| WP | Write Protect | Hardware lock for status register writes when WPEN=1; prevents accidental corruption of protection settings during power-up/down. |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer without resetting address counter; allows host MCU to service higher-priority interrupts mid-sequence. |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Configurable via status register to protect 0%, 25%, 50%, or 100% of memory - enables secure storage of factory-calibrated values while allowing runtime updates to user-configurable fields. |
| 32-byte Page Write | Reduces write time per byte by batching; avoids individual byte programming delays - improves throughput when writing sensor calibration tables or network MAC addresses. |
| HOLD Pin Functionality | Preserves internal state during serial transfer suspension - eliminates need for re-initialization or address retransmission after interrupt handling. |
| Self-timed Write Cycle | No external timing control needed; device asserts BUSY via RDY bit until completion - simplifies firmware design by removing polling complexity for fixed-duration operations. |
| Low-Voltage Operation | Valid down to 2.7V supply - supports battery-backed operation in portable equipment and brown-out resilience in industrial power rails. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping, scaling coefficients, and alarm thresholds in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via SPI during boot and runtime parameter updates. Use Value: Enables field-reprogrammable behavior without firmware reflashing; block protection prevents corruption of safety-critical calibration constants. | Use Scenario: Retaining sensor offset/gain corrections and patient-specific therapy parameters in portable infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Secure, long-life data vault interfaced to ARM Cortex-M host MCU over SPI at 10 MHz. Use Value: Meets 100-year data retention requirement for medical records; WP/HOLD pins support fail-safe update protocols during battery swaps. |
| Automotive Body Control Module | Smart Energy Meter Firmware Settings |
Use Scenario: Holding door lock logic states, mirror position presets, and lighting profiles in vehicle body control units operating across –40°C to +85°C. IC Role / Device Role / Timing Role: SPI EEPROM integrated into CAN-connected ECU for persistent user preference storage. Use Value: Qualified for automotive temperature range; 1M endurance supports lifetime seat/mirror adjustment logging without wear-out concerns. | Use Scenario: Storing tariff schedules, metering constants, and tamper-event logs in ANSI C12.22–compliant smart electricity meters. IC Role / Device Role / Timing Role: Trusted configuration store accessed during meter initialization and firmware OTA updates. Use Value: Hardware write protection (WP pin) prevents unauthorized modification of billing parameters; 32-byte page writes accelerate firmware patch application. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95320-WMN6TP | 32 Kbit SPI EEPROM, 2.5–5.5V supply, 20 MHz max clock, SOIC-8 package - lacks HOLD pin and supports only Mode 0. | No HOLD functionality limits use in interrupt-driven hosts; identical memory size and protection scheme suit simpler designs. | Select when HOLD is unused and board layout favors SOIC-8 over PDIP. |
| 25AA320A-I/P | 32 Kbit SPI EEPROM, 1.8–5.5V supply, 10 MHz max clock at 2.5V, PDIP-8 package - lower max speed but wider voltage range; includes WP/HOLD pins. | Better suited for battery-powered devices with variable supply; slower clock may impact boot time in high-speed systems. | Prefer for ultra-low-power applications where 10 MHz bandwidth suffices and 1.8V start-up is required. |
Compared with M95320-WMN6TP and 25AA320A-I/P, AT25320A-10PU-2.7 offers superior interrupt-handling capability via HOLD, guaranteed 20 MHz operation at 5V, and automotive-grade temperature support - making it optimal for real-time industrial and automotive control systems demanding deterministic serial access.
Availability
AT25320A-10PU-2.7 is available at Aetrix Electronics and suitable for industrial PLCs, medical instrumentation, automotive body control modules, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AT25320A-10PU-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and continues to manufacture and support its legacy serial EEPROM portfolio with full datasheet compliance and long-term availability commitments.
The AT25320A-10PU-2.7 belongs to the AT25xxxA family of SPI EEPROMs designed specifically for reliable, low-power nonvolatile storage in resource-constrained embedded systems where pin count, board space, and power budget are critical constraints.
FAQ
What is the maximum clock frequency supported by AT25320A-10PU-2.7?
The AT25320A-10PU-2.7 supports up to 20 MHz SCK frequency when operated at VCC = 5.0V. At lower voltages (2.7V), the maximum clock rate is reduced to 10 MHz, and at 1.8V it drops to 5 MHz - all specified in the AC Characteristics table. These limits ensure setup/hold timing margins are maintained across voltage and temperature ranges.
Does AT25320A-10PU-2.7 support SPI Mode 3 in addition to Mode 0?
Yes, AT25320A-10PU-2.7 explicitly supports both SPI Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 1), as confirmed in the Features section. This dual-mode capability allows seamless integration with diverse microcontroller platforms, including those requiring inverted clock polarity for noise immunity in electrically noisy environments.
How does the HOLD pin function during an active SPI read sequence?
During an active SPI read, asserting HOLD low while SCK is low suspends data output on SO and freezes the internal address counter. The master can resume transmission by bringing HOLD high while SCK remains low - no retransmission of op-code or address is needed. SO returns to high-impedance during HOLD, preserving bus integrity for other peripherals.
What memory protection options are available on AT25320A-10PU-2.7?
AT25320A-10PU-2.7 provides four levels of block write protection controlled by BP1/BP0 bits in the status register: none, 1/4 array (0xC00–0xFFF), 1/2 array (0x800–0xFFF), or full array (0x000–0xFFF). Protection is enforced regardless of WP pin state when WPEN = 1, and can be configured via WRSR instruction without requiring hardware changes.
Is AT25320A-10PU-2.7 RoHS compliant and lead-free?
Yes, AT25320A-10PU-2.7 is RoHS compliant and lead-free, as indicated by the "U" suffix in the part number per Atmel's ordering information notes. It meets JEDEC standards for green packaging and is supplied in halogen-free material formulation, satisfying environmental compliance requirements for global electronics manufacturing.
AT25320A-10PU-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 32Kbit
- Memory Organization:
- 4K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT25320A-10PU-2.7 FAQ
1.How can I place an order for AT25320A-10PU-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25320A-10PU-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25320A-10PU-2.7 reliable?
The price and inventory of AT25320A-10PU-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25320A-10PU-2.7 is usually 5 days.
3.What payment methods are accepted for AT25320A-10PU-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25320A-10PU-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25320A-10PU-2.7?
AT25320A-10PU-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25320A-10PU-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25320A-10PU-2.7?
For technical support, including AT25320A-10PU-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25320A-10PU-2.7 requirements.
6.How does Aetrix verify that AT25320A-10PU-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25320A-10PU-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25320A-10PU-2.7 meets industry standards.
7.What is the process for return or replacement of AT25320A-10PU-2.7?
All AT25320A-10PU-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25320A-10PU-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25320A-10PU-2.7 part is unused and in its original packaging.
Return procedure for AT25320A-10PU-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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