My Inquiry
My Account
Microchip Technology AT25320B-XHL-T
- Part No.:
- AT25320B-XHL-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT25320B-XHL-T.pdf
- Description:
- IC EEPROM 32KBIT SPI 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,240
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25320B-XHL-T from Microchip Technology (formerly Atmel) is a 32-kbit SPI serial EEPROM organized as 4,096 × 8-bit memory array, supporting SPI Modes 0 and 3, operating from 1.8V to 5.5V, with 20 MHz max clock rate at 5V and 5 ms max self-timed write cycle. It delivers high reliability for configuration storage in industrial controllers, IoT sensor nodes, and power management systems.
For engineers reviewing the AT25320B-XHL-T datasheet, AT25320B-XHL-T pinout, AT25320B-XHL-T application, or AT25320B-XHL-T equivalent, key selection criteria include its 8-lead TSSOP package, hardware/software write protection via WP pin and status register, 1,000,000 write endurance, 100-year data retention, and HOLD pin support for interruptible serial communication.
Technical Context
The AT25320B-XHL-T functions exclusively as an SPI slave device with dedicated SI (input) and SO (output) pins, requiring CS assertion and MSB-first 8-bit opcodes for all operations. Its internal architecture includes a 4,096-word memory array, status register with BP0/BP1 block protection bits, and independent WEN and WPEN control logic.
Write enable requires explicit WREN instruction before WRITE or WRSR; during active write cycles, only RDSR is accepted. Block protection supports four levels (none, 1/4, 1/2, full array), configurable via nonvolatile status register bits, while the HOLD pin suspends ongoing transfers without resetting sequence state when asserted low during SCK low time.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 32,768 bits (4,096 × 8-bit words) - fixed address space enabling compact firmware configuration storage without external address decoding. |
| Supply Voltage Range | 1.8 V to 5.5 V - supports direct interfacing with 1.8V, 3.3V, and 5V microcontrollers without level-shifting circuitry. |
| Max Clock Frequency | 20 MHz at 5V - enables fast read/write throughput (up to 2.5 MB/s theoretical) for time-critical parameter updates. |
| Write Cycle Time | 5 ms maximum - deterministic programming latency critical for real-time system recovery after power loss or reset. |
| Endurance & Retention | 1,000,000 write cycles / 100 years data retention - ensures long-term reliability in field-deployed equipment with frequent calibration or logging. |
| Operating Temperature | −40°C to +85°C - qualified for industrial environments including factory automation, energy meters, and outdoor gateways. |
| Interface Protocol | SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1) - interoperable with diverse MCU families including ARM Cortex-M, PIC, and legacy 68HC11. |
Pinout & Package
AT25320B-XHL-T is packaged in an 8-lead TSSOP (JEDEC MO-153, 4.4 mm body width), surface-mount package with 0.65 mm pitch, optimized for automated assembly and thermal performance in space-constrained PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be low to accept opcodes and data; high-impedance SO output when deasserted. |
| SCK | Serial Clock | Input-only synchronous timing reference; determines data transfer rate and sampling edge per SPI mode. |
| SI | Serial Data Input | MOSI path for opcodes, addresses, and write data; ignored during HOLD or when CS is high. |
| SO | Serial Data Output | MISO path for read data and status register contents; tri-stated when CS is high or HOLD is active. |
| WP | Write Protect | Hardware lock for status register writes when WPEN=1; prevents accidental corruption of protection settings during power transitions. |
| HOLD | Communication Suspend | Pauses ongoing SPI transaction without resetting internal state; allows host MCU to service higher-priority interrupts. |
| VCC | Power Supply | Single supply input (1.8–5.5 V); powers internal logic, memory array, and I/O buffers; decoupling capacitor required. |
| GND | Ground | Reference node for all signals and supply; must be low-impedance connection to minimize noise coupling into SO/SI paths. |
Key Features
| Feature | Design Value |
|---|---|
| 32-byte Page Write Mode | Enables burst programming of up to 32 contiguous bytes per write command, reducing total write time by >8× vs. byte-wise writes. |
| Four-Level Block Protection | Configurable via status register (BP1/BP0) to protect 0%, 25%, 50%, or 100% of memory - safeguards boot parameters and calibration constants. |
| Dual Write Protection Scheme | Combines hardware (WP pin) and software (WREN/WRSR) controls to prevent unintended writes during brown-out or firmware faults. |
| Self-Timed Internal Write Cycle | Eliminates need for external timing control or polling delay loops; RDSR bit 0 indicates completion for deterministic host synchronization. |
| Green RoHS-Compliant Packaging | NiPdAu lead finish in TSSOP package meets IPC/JEDEC standards for solderability, corrosion resistance, and environmental compliance. |
Applications
| Industrial PLC Configuration Storage | Smart Meter Calibration Data Retention |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and firmware update flags in programmable logic controllers deployed in factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via SPI during boot and runtime reconfiguration; operates at ≤10 MHz to match PLC MCU bus speed. Use Value: Ensures deterministic startup behavior and preserves operator-defined settings across 10+ year deployments without battery backup. |
Use Scenario: Holding meter-specific calibration coefficients, tariff schedules, and tamper-event logs in ANSI C12.22-compliant electricity meters. IC Role / Device Role / Timing Role: Secure parameter vault with hardware WP pin tied to system supervisor IC to prevent unauthorized modification during field servicing. Use Value: Meets ANSI C12.19 data integrity requirements with 1M-cycle endurance supporting daily log writes over 27-year lifetime. |
| IoT Edge Sensor Node Settings | Power Supply Sequencing Controller |
Use Scenario: Saving wireless network credentials, sensor offset corrections, and sleep interval configurations in battery-powered environmental monitors. IC Role / Device Role / Timing Role: Low-voltage (1.8V) SPI EEPROM interfaced directly to ultra-low-power MCU; accessed only during wake-up or OTA update. Use Value: Enables zero-battery-drain storage with <0.1 µA standby current at 1.8V, extending 10-year battery life in remote deployments. |
Use Scenario: Storing voltage ramp rates, fault thresholds, and channel enable states in multi-rail DC-DC sequencers for FPGA and ASIC power domains. IC Role / Device Role / Timing Role: Trusted configuration source read at power-on-reset; HOLD pin used to pause reads during critical rail stabilization phases. Use Value: Guarantees repeatable, glitch-free power sequencing across temperature extremes with verified −40°C to +85°C operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95320-DFMN6TP | 32-kbit SPI EEPROM, 2.5–5.5V supply, 20 MHz max, same 8-lead TSSOP package but with different pinout (SO/SI swapped vs. AT25320B-XHL-T). | Requires PCB layout revision due to SI/SO pin swap; lacks HOLD pin functionality - unsuitable where interruptible transfers are needed. | Select only if existing design uses M95xxx pinout and HOLD is unused; verify opcode compatibility (ST uses different status register map). |
| BR24G32FJ-3GE2 | 32-kbit I²C EEPROM (not SPI), 1.7–5.5V, 1 MHz max, 8-lead TSSOP, integrated write protect with lock bit. | I²C interface requires different MCU peripheral setup and timing budget; slower max speed limits high-throughput logging use cases. | Prefer for designs already using I²C buses and where SPI resource contention exists; avoid when migrating from existing SPI-based firmware. |
Compared with M95320-DFMN6TP and BR24G32FJ-3GE2, the AT25320B-XHL-T provides unique HOLD functionality and SPI Mode 0/3 flexibility, making it optimal for real-time embedded systems requiring interrupt-safe configuration access and broad MCU compatibility.
Availability
AT25320B-XHL-T is available at Aetrix Electronics and suitable for industrial PLCs, smart utility meters, IoT sensor nodes, and power supply sequencers requiring stable component supply across extended product lifecycles.
Supply support for AT25320B-XHL-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full technical and manufacturing continuity for the AT25xxx SPI EEPROM family.
The AT25320B-XHL-T belongs to Microchip's industrial-grade serial EEPROM product line, designed specifically for robust, low-power, nonvolatile data storage in harsh environments where long-term reliability and interface flexibility are critical.
FAQ
What is the maximum clock frequency supported by the AT25320B-XHL-T?
The AT25320B-XHL-T supports up to 20 MHz SCK frequency at VCC = 5.0 V, 10 MHz at 2.5–5.5 V, and 5 MHz at 1.8–5.5 V. These values are specified in Table 4-3 of the datasheet and reflect guaranteed AC timing margins across temperature and voltage ranges. The AT25320B-XHL-T must be operated within these limits to ensure reliable opcode recognition and data integrity during READ and WRITE sequences.
Does the AT25320B-XHL-T require an external pull-up resistor on the SO pin?
No, the AT25320B-XHL-T does not require an external pull-up on the SO pin. Its SO output is actively driven high or low during valid data transmission and enters high-impedance state when CS is high or HOLD is asserted. External pull-ups may cause bus contention or increased power consumption and are explicitly discouraged in the datasheet's "Electrical Characteristics" section.
How does the HOLD pin function during an active write cycle in the AT25320B-XHL-T?
The HOLD pin has no effect during an internal write cycle (tWC) in the AT25320B-XHL-T. Once the CS rising edge initiates programming, the device ignores HOLD until the write completes and returns to standby. HOLD is only functional during read, write-enable, or status register access sequences - never during active memory programming.
Can the AT25320B-XHL-T be used with a 1.8V-only microcontroller without level shifting?
Yes, the AT25320B-XHL-T is fully compatible with 1.8V-only MCUs. Its VIH min is VCC × 0.7 (≥1.26V at 1.8V) and VIL max is VCC × 0.3 (≤0.54V), matching standard 1.8V logic thresholds. All DC and AC characteristics-including tSU, tH, and fSCK-are validated down to 1.8V, confirming direct interface capability without level shifters.
What happens if an invalid opcode is sent to the AT25320B-XHL-T?
If an invalid opcode is received, the AT25320B-XHL-T ignores subsequent data bits on the SI line and holds the SO pin in high-impedance state until the next falling edge of CS. This behavior prevents spurious writes or status register corruption and allows the host MCU to detect protocol errors by monitoring SO state during command sequences.
AT25320B-XHL-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 32Kbit
- Memory Organization:
- 4K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT25320B-XHL-T FAQ
1.How can I place an order for AT25320B-XHL-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25320B-XHL-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25320B-XHL-T reliable?
The price and inventory of AT25320B-XHL-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25320B-XHL-T is usually 5 days.
3.What payment methods are accepted for AT25320B-XHL-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25320B-XHL-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25320B-XHL-T?
AT25320B-XHL-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25320B-XHL-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25320B-XHL-T?
For technical support, including AT25320B-XHL-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25320B-XHL-T requirements.
6.How does Aetrix verify that AT25320B-XHL-T is sourced from the original manufacturer or authorized distributors?
All AT25320B-XHL-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25320B-XHL-T meets industry standards.
7.What is the process for return or replacement of AT25320B-XHL-T?
All AT25320B-XHL-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25320B-XHL-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25320B-XHL-T part is unused and in its original packaging.
Return procedure for AT25320B-XHL-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25320B-XHL-T Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
