Microchip Technology AT25640A-10PU-1.8
- Part No.:
- AT25640A-10PU-1.8
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT25640A-10PU-1.8.pdf
- Description:
- IC EEPROM 64KBIT SPI 20MHZ 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:4,978
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25640A-10PU-1.8 from Microchip Technology (formerly Atmel) is a 64-Kbit SPI serial EEPROM organized as 8192 × 8-bit memory, supporting 1.8 V to 5.5 V supply operation, 20 MHz clock rate at 5 V, 32-byte page write mode, and hardware/software write protection via WP pin and status register. It serves as nonvolatile configuration storage in industrial controllers, sensor nodes, and power management ICs.
For engineers reviewing the AT25640A-10PU-1.8 datasheet, AT25640A-10PU-1.8 pinout, AT25640A-10PU-1.8 application, or AT25640A-10PU-1.8 equivalent, key selection criteria include low-voltage compatibility (1.8 V min), SPI Mode 0/3 support, block-level write protection granularity, self-timed 5 ms max write cycle, and JEDEC SOIC-8 packaging with RoHS-compliant lead finish.
Technical Context
The AT25640A-10PU-1.8 operates as a slave SPI peripheral with dedicated SI/SO lines, CS-controlled selection, and HOLD pin for transaction suspension without sequence reset. Its instruction set includes WREN/WRDI for write enable/disable, RDSR/WRSR for status register access, and READ/WRITE for memory access - all MSB-first with op-code–driven command decoding.
Block write protection is implemented via nonvolatile BP0/BP1 bits in the status register, enabling protection of 0%, 25%, 50%, or 100% of the memory array. Hardware write protection is conditional on WPEN bit = 1 and WP pin = low; WPEN=0 disables hardware protection regardless of WP state, allowing flexible system-level security design.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8192 × 8-bit), sufficient for firmware parameter tables or calibration data in space-constrained designs. |
| Supply Voltage Range | 1.8 V to 5.5 V - enables direct interface with 1.8 V logic families and backward compatibility with 3.3 V/5 V systems. |
| Max Clock Frequency | 20 MHz at VCC = 5 V - supports high-throughput configuration loading in real-time control loops. |
| Page Write Capacity | 32 bytes per write cycle - reduces software overhead by minimizing write instruction count for bulk updates. |
| Write Endurance | 1 million cycles - ensures reliable field recalibration or logging over 10+ years in industrial monitoring applications. |
| Data Retention | 100 years at +25 °C - guarantees long-term integrity of stored calibration coefficients or security keys without refresh. |
| Operating Temperature | –40 °C to +85 °C - qualified for industrial-grade embedded systems including motor drives and PLC I/O modules. |
Pinout & Package
AT25640A-10PU-1.8 is supplied in an 8-lead JEDEC SOIC package (8S1), 0.150" wide body, RoHS-compliant, green plastic with NiPdAu lead finish. Pin 1 is marked with a notch or dot; device orientation follows standard SOIC conventions.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable: asserts SPI communication window; high-Z SO when CS high prevents bus contention. |
| SCK | Serial Clock | Master-generated clock input; timing-critical path requiring controlled trace impedance and minimal skew. |
| SI | Serial Data Input | Receives op-codes, addresses, and write data; sampled on SCK rising edge in Mode 0. |
| SO | Serial Data Output | Drives read data and status bits; high-impedance when CS high or during HOLD assertion. |
| WP | Write Protect | Hardware lock: blocks status register writes when WPEN=1 and WP=low; configurable via WRSR. |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer without resetting address counter; requires SCK low during assertion. |
| VCC | Power Supply | 1.8–5.5 V input; decoupling capacitor (0.1 µF) required within 10 mm of pin for noise immunity. |
| GND | Ground Reference | Return path for all I/O and core logic; must be connected to system ground plane with low-inductance path. |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode 0 & 3 Compatibility | Supports both clock polarity/phase variants, enabling interoperability with diverse microcontrollers (e.g., STM32, PIC, MSP430). |
| Four-Tier Block Protection | BP0/BP1 bits allow selective locking of 0%, 25%, 50%, or 100% of memory - isolates critical boot parameters from runtime updates. |
| Self-Timed Write Cycle | 5 ms maximum internal erase/write time eliminates need for external delay timers or polling overhead in host firmware. |
| Dual Write Protection Mechanism | Combines hardware (WP pin) and software (WRSR + WREN) controls - satisfies functional safety requirements for redundant data integrity. |
| Low Standby Current | < 0.1 µA at 1.8 V - extends battery life in energy-harvesting sensor nodes and portable diagnostic tools. |
Applications
| Industrial Sensor Calibration | Motor Drive Configuration Storage |
|---|---|
|
Use Scenario: Storing temperature-compensated offset/gain coefficients for analog front-end sensors in factory automation systems. IC Role / Device Role / Timing Role: Nonvolatile parameter repository accessed during power-up initialization and periodic recalibration routines. Use Value: Enables field-adjustable accuracy without firmware reflash; 100-year retention ensures calibration validity across equipment lifetime. |
Use Scenario: Holding torque curve profiles, current limit thresholds, and commutation timing offsets in BLDC motor controllers. IC Role / Device Role / Timing Role: SPI-configurable memory mapped into MCU's peripheral address space for runtime parameter lookup. Use Value: 32-byte page writes reduce update latency during dynamic profile switching; 1.8 V operation supports low-power standby modes. |
| Smart Energy Meter Firmware Settings | Medical Device Safety Parameters |
|
Use Scenario: Securing tariff schedules, pulse constants, and tamper-detection flags in ANSI C12.19-compliant electricity meters. IC Role / Device Role / Timing Role: Secure configuration store with hardware write protection preventing unauthorized parameter modification. Use Value: WP pin tied to meter housing switch provides physical tamper response; BP bits lock critical billing registers against firmware bugs. |
Use Scenario: Archiving FDA-mandated safety limits (e.g., maximum output voltage, thermal shutdown thresholds) in portable infusion pumps. IC Role / Device Role / Timing Role: Fail-safe memory element storing immutable safety-critical values verified at boot and runtime. Use Value: 1 million endurance cycles support frequent safety audits; 100-year retention meets ISO 13485 long-term recordkeeping requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95640-DWDW3TP/K | 64 Kbit SPI EEPROM, 2.5–5.5 V supply, 20 MHz max, SOIC-8, but lacks HOLD pin and has no 1.8 V operation. | Not suitable for ultra-low-voltage systems or designs requiring transaction suspension without reset. | Select only if system operates ≥2.5 V and HOLD functionality is unused. |
| 25AA640A-I/P | 64 Kbit SPI EEPROM, 1.8–5.5 V, SOIC-8, includes HOLD and WP pins, but rated for –40°C to +125°C and uses different status register layout. | Better suited for automotive under-hood applications; requires firmware adaptation for BP bit mapping. | Prefer for extended temperature range needs; verify status register compatibility before firmware porting. |
Compared with M95640-DWDW3TP/K and 25AA640A-I/P, AT25640A-10PU-1.8 uniquely combines 1.8 V operation, HOLD functionality, and JEDEC SOIC-8 packaging with documented 100-year data retention - making it optimal for industrial IoT nodes where voltage scalability and transaction robustness are critical.
Availability
AT25640A-10PU-1.8 is available at Aetrix Electronics and suitable for industrial sensor calibration, motor drive configuration storage, smart energy meter firmware settings, and medical device safety parameter archiving requiring stable component supply across multi-year production cycles.
Supply support for AT25640A-10PU-1.8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT25xxx family of serial EEPROMs.
The AT25640A-10PU-1.8 belongs to Microchip's legacy serial EEPROM product line, designed specifically for low-power, low-voltage embedded systems requiring reliable nonvolatile storage with SPI interface simplicity and robust data protection.
FAQ
What is the minimum operating voltage for AT25640A-10PU-1.8?
The AT25640A-10PU-1.8 supports true 1.8 V operation, with guaranteed functionality down to 1.8 V across the full industrial temperature range (–40°C to +85°C). This allows direct interfacing with 1.8 V microcontrollers and low-power ASICs without level-shifting circuitry. The device remains fully compliant with SPI timing specifications at 1.8 V, though maximum clock frequency is reduced compared to 5 V operation.
Does AT25640A-10PU-1.8 support SPI Mode 3 (CPOL=1, CPHA=1)?
Yes, AT25640A-10PU-1.8 explicitly supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1), as confirmed in the official datasheet Features section. This dual-mode capability ensures compatibility with microcontrollers that default to inverted clock polarity, such as certain NXP LPC and Renesas RX series devices, without requiring hardware modifications or software workarounds.
How does the WRITE PROTECT (WP) pin function in AT25640A-10PU-1.8?
In AT25640A-10PU-1.8, the WP pin provides hardware-level write inhibition when the WPEN bit in the status register is set to "1" and WP is driven low. When active, it blocks all writes to the status register (including BP bits and WPEN itself) and to memory regions covered by block protection. If WPEN=0, the WP pin is ignored - enabling flexible system integration where WP may be tied to ground without disabling configuration updates.
What is the maximum write cycle time for AT25640A-10PU-1.8?
The maximum write cycle time for AT25640A-10PU-1.8 is 5 ms, applicable across the full 1.8 V to 5.5 V supply range and –40°C to +85°C temperature range. This self-timed internal cycle eliminates the need for host-side delay loops or busy-wait polling; instead, firmware can issue RDSR commands to check the RDY bit (bit 0) and proceed only when the write completes.
Is AT25640A-10PU-1.8 RoHS-compliant and halogen-free?
Yes, AT25640A-10PU-1.8 is RoHS-compliant and halogen-free, as indicated by the "U" suffix in its ordering code. It features a green plastic package with NiPdAu lead finish, meeting JEDEC standards for environmentally conscious manufacturing. Full compliance documentation, including material declarations and test reports, is available through Microchip's product change notifications and quality portal.
AT25640A-10PU-1.8 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT25640A-10PU-1.8 FAQ
1.How can I place an order for AT25640A-10PU-1.8 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25640A-10PU-1.8 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25640A-10PU-1.8 reliable?
The price and inventory of AT25640A-10PU-1.8 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25640A-10PU-1.8 is usually 5 days.
3.What payment methods are accepted for AT25640A-10PU-1.8?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25640A-10PU-1.8 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25640A-10PU-1.8?
AT25640A-10PU-1.8 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25640A-10PU-1.8 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25640A-10PU-1.8?
For technical support, including AT25640A-10PU-1.8 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25640A-10PU-1.8 requirements.
6.How does Aetrix verify that AT25640A-10PU-1.8 is sourced from the original manufacturer or authorized distributors?
All AT25640A-10PU-1.8 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25640A-10PU-1.8 meets industry standards.
7.What is the process for return or replacement of AT25640A-10PU-1.8?
All AT25640A-10PU-1.8 units undergo pre-shipment inspection (PSI). If there is an issue with AT25640A-10PU-1.8, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25640A-10PU-1.8 part is unused and in its original packaging.
Return procedure for AT25640A-10PU-1.8:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25640A-10PU-1.8 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

