Microchip Technology AT25640AN-10SI-2.7
- Part No.:
- AT25640AN-10SI-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25640AN-10SI-2.7.pdf
- Description:
- IC EEPROM 64KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT25640AN-10SI-2.7 from Microchip Technology (formerly Atmel) is a 64 Kbit SPI serial EEPROM organized as 8192 × 8-bit memory, operating from 2.7V to 5.5V, supporting 20 MHz clock rate at 5V, with 32-byte page write capability and hardware/software write protection via WP pin and status register. It serves as nonvolatile configuration storage in automotive body control modules.
For engineers reviewing the AT25640AN-10SI-2.7 datasheet, AT25640AN-10SI-2.7 pinout, AT25640AN-10SI-2.7 application, or AT25640AN-10SI-2.7 equivalent, key selection criteria include industrial temperature range (−40°C to +85°C), JEDEC SOIC-8 package compatibility, SPI Mode 0/3 support, 5 ms max self-timed write cycle, and block write protection granularity for safety-critical firmware parameter storage.
Technical Context
The AT25640AN-10SI-2.7 implements a synchronous serial peripheral interface (SPI) slave architecture with separate SI/SO lines, MSB-first data transfer, and CS-driven command framing. It uses an 8-bit instruction register with op-codes for WREN, WRITE, RDSR, and WRSR to manage memory access and protection state.
Its internal write cycle is fully self-timed with no external erase step required; the READY/BUSY bit (RDY) in the status register indicates completion. Block protection is implemented via nonvolatile BP0/BP1 bits controlling 1/4, 1/2, or full array lock, while WPEN enables or disables hardware write protection through the WP pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8192 × 8-bit), enabling storage of boot parameters, calibration data, or device IDs in space-constrained designs |
| Supply Voltage Range | 2.7V to 5.5V - supports direct interfacing with 3.3V and 5V microcontrollers without level-shifting |
| Max Clock Frequency | 20 MHz at VCC = 5V - enables fast configuration reads during system startup |
| Page Write Size | 32 bytes - reduces write latency versus byte-write by batching related settings (e.g., sensor offset + gain) |
| Write Cycle Time | 5 ms maximum - deterministic timing for firmware update routines and watchdog-triggered save operations |
| Endurance & Retention | 1 million write cycles / 100-year data retention - suitable for logging applications with frequent updates |
| Operating Temperature | −40°C to +85°C - qualified for under-hood automotive and industrial control environments |
Pinout & Package
AT25640AN-10SI-2.7 is housed in an 8-lead JEDEC SOIC (8S1) package, 0.150" wide, with standard gull-wing leads and 1.27 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must be low to accept instructions; high-Z SO when deasserted |
| SCK | Serial Clock | Input-only clock synchronized to master; defines timing for SI sampling and SO output |
| SI | Serial Data Input | Accepts op-code, address, and data; ignored during HOLD or when CS is high |
| SO | Serial Data Output | Tri-state output delivering read data or status bits; high-Z when CS high or HOLD active |
| WP | Write Protect | Hardware lock for status register and protected memory blocks when WPEN=1 and WP=low |
| HOLD | Communication Suspend | Pauses ongoing SPI transaction without resetting address counter; requires SCK low to assert |
| VCC | Power Supply | Primary supply rail (2.7–5.5V); powers internal logic and memory array |
| GND | Ground | Reference return path for all I/O and internal circuitry |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode 0 & 3 Support | Interoperates with 68HC11, PIC, ARM Cortex-M, and other common MCU SPI peripherals without mode translation logic |
| Block Write Protection | Configurable 1/4, 1/2, or full-array lock via nonvolatile BP0/BP1 bits - prevents accidental overwrite of critical calibration sectors |
| Hardware + Software Write Protection | WP pin and WRSR instruction jointly enforce multi-layer security: WP blocks status register writes when enabled, while software controls memory segment locks |
| Self-timed Write Cycle | No external timing control needed; RDY bit allows polling instead of fixed delays - simplifies firmware and improves system responsiveness |
| Automotive Grade Packaging | JEDEC SOIC-8 with lead-free/halogen-free construction meets AEC-Q200 stress test requirements for vibration, thermal cycling, and humidity resistance |
Applications
| Automotive Body Control Unit | Industrial PLC Configuration Storage |
|---|---|
Use Scenario: Storing door lock actuator calibration values and seat position presets across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile configuration EEPROM interfaced to an 8-bit MCU via SPI Mode 0 at 10 MHz. Use Value: Enables field-updatable calibration without requiring battery-backed SRAM; 1M endurance supports 10+ years of daily reprogramming. | Use Scenario: Retaining I/O mapping tables and alarm thresholds after power loss in modular automation controllers. IC Role / Device Role / Timing Role: SPI slave providing persistent parameter storage for real-time control firmware. Use Value: 32-byte page writes reduce configuration save time by 75% vs. byte-wise writes; −40°C to +85°C rating ensures reliability in factory-floor enclosures. |
| Medical Infusion Pump Settings | Smart Energy Meter Firmware Parameters |
Use Scenario: Securing drug delivery profiles and user-access levels against unauthorized modification. IC Role / Device Role / Timing Role: Protected memory node using WP pin hardwired to system security controller and BP1/BP0 set to 1/2-array lock. Use Value: Hardware-enforced write protection prevents tampering during operation; 100-year data retention guarantees lifetime device integrity. | Use Scenario: Storing tariff schedules, metering constants, and communication keys in utility-grade electricity meters. IC Role / Device Role / Timing Role: SPI EEPROM accessed during cold start to load operational parameters before metrology engine initialization. Use Value: 20 MHz read speed at 5V enables full parameter load in <100 µs; extended temperature grade supports outdoor pole-mount installations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95640-DW | STMicroelectronics 64 Kbit SPI EEPROM; identical 8-lead SOIC package, 2.5–5.5V supply, 20 MHz max clock, but uses different status register bit layout and lacks HOLD pin | Supports same automotive/industrial use cases but requires firmware adaptation for status register interpretation and no suspend capability during SPI transfers | Select when HOLD functionality is unused and existing ST ecosystem integration reduces qualification effort |
| BR24G64FJ-WE2 | Rohm 64 Kbit SPI EEPROM; 1.7–5.5V supply, 10 MHz max clock, 8-lead TSSOP package, built-in error correction code (ECC), no WP/HOLD pins | Lower speed and no hardware write protect limit suitability for safety-critical systems requiring deterministic fault detection and physical lockout | Prefer where ECC-assisted reliability outweighs need for hardware protection and higher throughput |
Compared with M95640-DW and BR24G64FJ-WE2, AT25640AN-10SI-2.7 uniquely combines HOLD pin support for interrupt-safe SPI transactions, dedicated WP pin with configurable WPEN, and full 20 MHz performance at 5V - making it optimal for real-time embedded systems requiring both speed and robust data integrity controls.
Availability
AT25640AN-10SI-2.7 is available at Aetrix Electronics and suitable for automotive body electronics, industrial programmable logic controllers, and medical device configuration storage requiring stable component supply, long-term lifecycle assurance, and AEC-Q200-compliant packaging.
Supply support for AT25640AN-10SI-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with broad industrial and automotive qualification expertise.
The AT25640AN-10SI-2.7 belongs to Microchip's legacy Atmel SPI EEPROM product line, designed specifically for reliable, low-power nonvolatile data storage in resource-constrained embedded systems requiring SPI interface simplicity and robust write protection.
FAQ
What is the memory organization of the AT25640AN-10SI-2.7?
The AT25640AN-10SI-2.7 contains 64 Kbit of serial EEPROM memory organized as 8192 words of 8 bits each (8192 × 8). This structure supports byte-addressable reads and writes, with address bits A12–A0 defined per the datasheet. The AT25640AN-10SI-2.7 uses a linear addressing scheme compatible with standard SPI memory access protocols used in microcontroller firmware.
Does the AT25640AN-10SI-2.7 support both SPI Mode 0 and Mode 3?
Yes, the AT25640AN-10SI-2.7 explicitly supports SPI Modes 0 (CPOL = 0, CPHA = 0) and 3 (CPOL = 1, CPHA = 1), as confirmed in its official features list. This dual-mode capability allows seamless integration with diverse host processors including legacy 68HC11 derivatives and modern ARM-based MCUs. The AT25640AN-10SI-2.7 does not support Mode 1 or Mode 2.
How does hardware write protection work on the AT25640AN-10SI-2.7?
Hardware write protection on the AT25640AN-10SI-2.7 is controlled by the WP pin and the WPEN bit in the status register. When WPEN = 1 and WP is driven low, writes to the status register and block-protected memory segments are disabled. If WPEN = 0, the WP pin is ignored. The AT25640AN-10SI-2.7 requires explicit WREN before any write, and WRDI resets the latch - ensuring layered security.
What is the maximum clock frequency for the AT25640AN-10SI-2.7 at 3.3V operation?
At VCC = 3.3V, the AT25640AN-10SI-2.7 supports a maximum SCK frequency of 10 MHz, as specified in the AC Characteristics table for the 2.7–5.5V voltage range. This is lower than its 20 MHz rating at 5V but remains sufficient for most configuration and logging tasks. The AT25640AN-10SI-2.7 maintains full functionality including page write and status register access at this speed.
Is the AT25640AN-10SI-2.7 qualified for automotive applications?
Yes, the AT25640AN-10SI-2.7 is offered in automotive-grade variants with extended temperature range (−40°C to +125°C) and lead-free/halogen-free construction. While the -10SI-2.7 suffix denotes industrial temperature (−40°C to +85°C), its underlying design, packaging (JEDEC SOIC-8), and qualification testing align with AEC-Q200 requirements. The AT25640AN-10SI-2.7 is widely deployed in automotive body control modules and infotainment subsystems.
AT25640AN-10SI-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25640AN-10SI-2.7 FAQ
1.How can I place an order for AT25640AN-10SI-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25640AN-10SI-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25640AN-10SI-2.7 reliable?
The price and inventory of AT25640AN-10SI-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25640AN-10SI-2.7 is usually 5 days.
3.What payment methods are accepted for AT25640AN-10SI-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25640AN-10SI-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25640AN-10SI-2.7?
AT25640AN-10SI-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25640AN-10SI-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25640AN-10SI-2.7?
For technical support, including AT25640AN-10SI-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25640AN-10SI-2.7 requirements.
6.How does Aetrix verify that AT25640AN-10SI-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25640AN-10SI-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25640AN-10SI-2.7 meets industry standards.
7.What is the process for return or replacement of AT25640AN-10SI-2.7?
All AT25640AN-10SI-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25640AN-10SI-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25640AN-10SI-2.7 part is unused and in its original packaging.
Return procedure for AT25640AN-10SI-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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