Microchip Technology AT25640AN-10SU-2.7
- Part No.:
- AT25640AN-10SU-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25640AN-10SU-2.7.pdf
- Description:
- IC EEPROM 64KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,343
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Product details
Overview
AT25640AN-10SU-2.7 from Microchip Technology (formerly Atmel) is a 64 Kbit SPI serial EEPROM organized as 8192 × 8-bit memory, supporting 2.7–5.5 V operation, 20 MHz clock rate at 5 V, 32-byte page write mode, and hardware/software write protection via WP pin and status register. It serves as nonvolatile configuration storage in industrial control modules requiring low-voltage reliability and SPI interface compatibility with microcontrollers such as the 68HC11.
For engineers reviewing the AT25640AN-10SU-2.7 datasheet, AT25640AN-10SU-2.7 pinout, AT25640AN-10SU-2.7 application, or AT25640AN-10SU-2.7 equivalent, key selection criteria include verified 2.7 V minimum supply support, JEDEC SOIC-8 package dimensions, block write protection granularity (1/4, 1/2, or full array), HOLD pin suspend functionality, and 1 million write cycle endurance.
Technical Context
The AT25640AN-10SU-2.7 implements a synchronous SPI slave interface compliant with Modes 0 and 3, using separate SI/SO lines and CS-controlled access. Its internal architecture includes an 8-bit instruction register, nonvolatile status register (BP0/BP1/WPEN/RDY/WEN), and automatic address incrementing during page writes.
Write operations require explicit WREN instruction prior to WRITE or WRSR; self-timed internal write cycles complete in ≤5 ms. Block protection is enforced by BP0/BP1 bits mapping to fixed address ranges (e.g., 0x1800–0x1FFF for full-array lock), while WP pin behavior is gated by WPEN bit state per Table 3-5.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8192 × 8-bit), enabling storage of firmware parameters or calibration data in space-constrained embedded systems |
| Supply Voltage Range | 2.7 V to 5.5 V - supports direct integration into 3.3 V and 5 V logic domains without level-shifting |
| Max Clock Frequency | 20 MHz at VCC = 5 V - enables high-throughput configuration reads during system boot |
| Page Write Size | 32 bytes - minimizes write latency versus byte-write EEPROMs while preserving endurance |
| Endurance | 1 million write cycles - ensures long-term reliability in field-updatable devices with frequent parameter logging |
| Data Retention | 100 years at +25 °C - guarantees persistent storage across product lifecycle without refresh |
| Operating Temperature | –40 °C to +85 °C - validated for industrial-grade deployment in motor drives and PLCs |
Pinout & Package
AT25640AN-10SU-2.7 is packaged in an 8-lead JEDEC SOIC (8S1) with 150-mil body width, RoHS-compliant lead finish, and standard gull-wing lead form factor compatible with automated SMT assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; device ignores SI and tri-states SO when CS is high |
| SCK | Serial Clock | Input-only clock synchronized to master; timing critical for tWH/tWL compliance per Table 1-3 |
| SI | Serial Data Input | Receives op-codes, addresses, and data; MSB-first transmission required |
| SO | Serial Data Output | Tri-state output delivering read data or status bits; high-impedance when CS high or HOLD active |
| GND | Ground Reference | Primary return path for VCC and I/O signals; must be low-inductance connection for noise immunity |
| VCC | Power Supply | 2.7–5.5 V input; decoupling capacitor (0.1 µF) required within 10 mm of pin |
| WP | Write Protect | Hardware lock for status register and protected memory blocks when WPEN = 1 and WP = low |
| HOLD | Communication Suspend | Pauses ongoing SPI transfer without resetting sequence; requires SCK low during assertion |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode 0 & 3 Support | Interoperates with diverse microcontrollers including 68HC11 and ARM Cortex-M series without protocol translation |
| Block Write Protection | Four configurable protection levels (none, 1/4, 1/2, full array) prevent accidental overwrites of critical firmware sections |
| 32-byte Page Write | Reduces average write time by 96% vs. byte-write mode for multi-byte updates, extending effective endurance |
| HOLD Pin Functionality | Enables real-time interrupt handling in host MCU without losing SPI context or requiring reinitialization |
| WPEN-Controlled Hardware Lock | Allows safe installation in systems with grounded WP pin while retaining ability to configure protection via software |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Retention |
|---|---|
Use Scenario: Storing I/O mapping tables and alarm thresholds in programmable logic controllers operating in factory environments with voltage fluctuations. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via SPI during power-up and runtime parameter updates. Use Value: 2.7 V minimum supply tolerance ensures reliable operation during brown-out conditions; 100-year data retention eliminates recalibration service intervals. |
Use Scenario: Holding sensor offset/gain coefficients and patient-specific therapy settings in portable infusion pumps certified to IEC 60601-1. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store interfaced to safety-critical microcontroller via isolated SPI bus. Use Value: Block write protection prevents corruption of calibrated values during firmware updates; WP pin hardening meets medical EMC immunity requirements. |
| Automotive Body Control Module (BCM) | Smart Energy Meter Firmware Parameters |
Use Scenario: Saving door lock actuation history and lighting profiles in automotive BCMs exposed to –40 °C to +85 °C ambient. IC Role / Device Role / Timing Role: AEC-Q100 qualified (per family documentation) serial EEPROM for infrequent but mission-critical NVM writes. Use Value: 1 million write cycles support 10+ years of daily usage; HOLD pin allows seamless interruption during CAN bus arbitration delays. |
Use Scenario: Storing tariff schedules, meter ID, and cryptographic keys in ANSI C12.22-compliant smart meters deployed in utility grids. IC Role / Device Role / Timing Role: Cryptographically secured configuration store accessed only during authenticated firmware update windows. Use Value: Dual protection (WP pin + WRSR software lock) prevents unauthorized modification of billing parameters; SOI-compatible SOIC-8 eases conformal coating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95640-DW | STMicroelectronics 64 Kbit SPI EEPROM; identical 8-lead SOIC package, 2.5–5.5 V range, but max clock 20 MHz only at 5 V (10 MHz at 2.5 V) | Lower 2.5 V min supply enables single-cell Li-ion backup; lacks HOLD pin for suspend capability | Select when battery-backed operation below 2.7 V is required and HOLD functionality is unnecessary |
| 25AA640A-I/SN | Microchip 64 Kbit SPI EEPROM; same SOIC-8 package and 1.8–5.5 V range, but rated for industrial temp only (–40 °C to +85 °C), no automotive qualification | Identical pinout and instruction set; differs in test screening-no AEC-Q100 validation for automotive use | Select for cost-sensitive industrial designs where automotive qualification is not mandated |
Compared with M95640-DW and 25AA640A-I/SN, the AT25640AN-10SU-2.7 uniquely combines guaranteed 2.7 V operation, HOLD pin support, and documented automotive suitability-making it optimal for systems requiring robust suspend-on-interrupt behavior and extended temperature resilience without voltage margin compromise.
Availability
AT25640AN-10SU-2.7 is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, automotive body electronics, and smart metering applications requiring stable component supply, long-term obsolescence management, and RoHS-compliant sourcing.
Supply support for AT25640AN-10SU-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full technical and manufacturing continuity for the AT25xxx family of serial EEPROMs.
The AT25640AN-10SU-2.7 belongs to Microchip's legacy Atmel serial EEPROM product line, engineered for low-power, low-voltage embedded systems requiring SPI-compatible nonvolatile storage with robust data integrity features.
FAQ
What is the minimum operating voltage for the AT25640AN-10SU-2.7?
The AT25640AN-10SU-2.7 operates down to 2.7 V, as indicated by the "-2.7" suffix in its part number and confirmed in DC Characteristics Table 1-2 (VCC2 min = 2.7 V). This allows direct interface with 3.3 V systems without regulators and ensures functional stability during brown-out events common in industrial power rails.
Does the AT25640AN-10SU-2.7 support SPI Mode 3 (CPOL=1, CPHA=1)?
Yes, the AT25640AN-10SU-2.7 explicitly supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1), as stated in the Features section. This dual-mode capability enables interoperability with microcontrollers like certain PIC and AVR families that default to Mode 3 for noise immunity in electrically noisy environments.
How does block write protection work on the AT25640AN-10SU-2.7?
Block write protection on the AT25640AN-10SU-2.7 is controlled by BP0 and BP1 bits in the status register. These bits define four protection levels: none, lower 1/4 (0x1800–0x1FFF), lower 1/2 (0x1000–0x1FFF), or full array (0x0000–0x1FFF). Protection is enforced during WRITE instructions and cannot be overridden while active.
Can the AT25640AN-10SU-2.7 be used in automotive applications?
Yes-the AT25640AN-10SU-2.7 is explicitly listed as "Available in Automotive" in the Features section and shares the same industrial temperature range (–40 °C to +85 °C) and qualification pedigree as Atmel's automotive-grade serial EEPROMs. While not individually AEC-Q100 certified, its family-level automotive suitability supports under-hood and body-control module deployments.
What is the purpose of the HOLD pin on the AT25640AN-10SU-2.7?
The HOLD pin on the AT25640AN-10SU-2.7 suspends ongoing SPI communication without resetting the serial sequence. When asserted low while SCK is low, it places SO in high-impedance state and ignores SI inputs-allowing the host MCU to service higher-priority interrupts and resume exactly where the transfer left off, preserving timing-critical data integrity.
AT25640AN-10SU-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25640AN-10SU-2.7 FAQ
1.How can I place an order for AT25640AN-10SU-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25640AN-10SU-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25640AN-10SU-2.7 reliable?
The price and inventory of AT25640AN-10SU-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25640AN-10SU-2.7 is usually 5 days.
3.What payment methods are accepted for AT25640AN-10SU-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25640AN-10SU-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25640AN-10SU-2.7?
AT25640AN-10SU-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25640AN-10SU-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25640AN-10SU-2.7?
For technical support, including AT25640AN-10SU-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25640AN-10SU-2.7 requirements.
6.How does Aetrix verify that AT25640AN-10SU-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25640AN-10SU-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25640AN-10SU-2.7 meets industry standards.
7.What is the process for return or replacement of AT25640AN-10SU-2.7?
All AT25640AN-10SU-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25640AN-10SU-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25640AN-10SU-2.7 part is unused and in its original packaging.
Return procedure for AT25640AN-10SU-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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