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Microchip Technology AT25640B-XPDGV-T

Name: AT25640B-XPDGV-T
Brand: Microchip Technology
SKU: AT25640B-XPDGV-T
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AT25640B-XPDGV-T

Manufacturer:: Microchip Technology

Category:: Memory

Package:: 8-TSSOP (0.173", 4.40mm Width)

Datasheet:: AT25640B-XPDGV-T.pdf

Description:: IC EEPROM 64KBIT SPI 5MHZ 8TSSOP

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Product details

Overview

AT25640B-XPDGV-T from Microchip Technology is a 64 Kbit (8,192 × 8) SPI Serial EEPROM optimized for automotive-grade nonvolatile data storage. It operates across 1.7V–5.5V supply, supports SPI Modes 0 and 3, delivers up to 5 MHz clock rate at 5V, features 32-byte page write capability, and is AEC-Q100 Grade 3 qualified (−40°C to +85°C) for use in engine control units, ADAS sensor modules, and body electronics.

For engineers reviewing the AT25640B-XPDGV-T datasheet, AT25640B-XPDGV-T pinout, AT25640B-XPDGV-T application, or AT25640B-XPDGV-T equivalent, key selection criteria include its automotive temperature rating, hardware/software write protection via WP and STATUS register, 1,000,000 write endurance, 100-year data retention, and compatibility with microcontroller SPI masters requiring robust, low-voltage EEPROM in space-constrained layouts.

Technical Context

The AT25640B-XPDGV-T implements a synchronous SPI slave interface with fixed MSb-first data framing, rising-edge input sampling on SI, and falling-edge output valid on SO. Its internal architecture includes a high-voltage generation circuit for EEPROM programming, a status register with nonvolatile BP1/BP0 block protection bits, and dedicated WP and HOLD pins enabling hardware-level suspend and write inhibit independent of software state.

It supports dual voltage grades: Grade 3 (1.7V–5.5V, −40°C to +85°C) and Grade 1 (2.5V–5.5V, −40°C to +125°C); the XPDGV-T suffix confirms Grade 3 qualification and 8-lead TSSOP packaging. Write operations are self-timed with ≤5 ms maximum cycle time, and standby current is as low as 0.1 µA at 1.7V.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Size	64 Kbits (8,192 × 8), organized as 8,192 addressable bytes - enables firmware parameter storage, calibration data logging, and configuration persistence in resource-limited ECUs.
Supply Voltage Range	1.7V to 5.5V - supports direct interfacing with 1.8V, 3.3V, and 5V microcontrollers without level-shifting in automotive domains.
Max Clock Frequency	5 MHz at VCC = 5.0V - allows fast read/write bursts (e.g., 32-byte page writes in <100 µs) while maintaining timing margin under EMI stress.
Write Endurance	1,000,000 cycles - ensures reliable operation over 15+ years of daily reconfiguration in telematics or infotainment systems.
Data Retention	100 years at TA = 55°C - guarantees long-term integrity of safety-critical calibration tables and VIN/ECU ID storage without refresh.
Temperature Grade	AEC-Q100 Grade 3 (−40°C to +85°C) - validated for cabin and chassis-mounted applications where extended ambient range is required but full Grade 1 is not mandated.
Page Write Size	32 bytes - minimizes bus occupancy during bulk updates and aligns with typical CAN/FlexRay message payload boundaries.

Pinout & Package

AT25640B-XPDGV-T is housed in an 8-lead Thin Shrink Small Outline Package (TSSOP), measuring 4.4 mm × 3.0 mm × 1.2 mm, with gull-wing leads and RoHS-compliant matte tin plating. The package is pin-compatible with SOIC-8 and UDFN-8 variants of the AT25xxxB family.

Pin/Terminal	Circuit Role	Design Meaning
CS (Pin 1)	Chip Select	Active-low enable signal; must be driven low before SCK edge to initiate SPI transaction; requires pull-up resistor (≤10 kΩ) tied to VCC for robust power-up behavior.
SO (Pin 2)	Serial Data Output	Tri-state output delivering MSb-first data on falling SCK edge; enters high-impedance when CS is high or HOLD is asserted.
WP (Pin 3)	Write-Protect	Hardware lock for STATUS register writes when WPEN=1; can be tied low for permanent protection or controlled dynamically to prevent accidental writes during system reset.
GND (Pin 4)	Ground Reference	Primary return path for VCC and all I/O; must be connected directly to system ground plane to minimize noise coupling into sensitive EEPROM array.
SI (Pin 5)	Serial Data Input	Receives opcodes, addresses, and data on rising SCK edge; latched synchronously to avoid metastability in noisy automotive environments.
SCK (Pin 6)	Serial Clock Input	Asynchronous master-generated clock; supports idle-high (Mode 3) or idle-low (Mode 0); timing margins validated per AEC-Q100 for jitter tolerance.
HOLD (Pin 7)	Suspend Control	Pauses ongoing SPI transfer without resetting state machine; used to yield bus access to higher-priority peripherals while preserving command context.
VCC (Pin 8)	Power Supply	Single-supply input supporting 1.7V–5.5V; internal POR circuit enforces 100 µs delay after stable VCC before accepting commands.

Key Features

Feature	Design Value
SPI Mode 0 & 3 Compatibility	Enables seamless integration with diverse MCU families (e.g., Renesas RH850, NXP S32K, Infineon AURIX) without protocol translation or firmware adaptation.
Block Write Protection	Configurable 1/4, 1/2, or full memory array lock via STATUS register BP1/BP0 bits - prevents corruption of critical boot parameters while allowing runtime update of user settings.
Hardware + Software Write Protection	Combines dedicated WP pin (for board-level security) with WREN/WRDI instructions and STATUS register control - satisfies ISO 26262 ASIL-B functional safety requirements for data integrity.
Automotive AEC-Q100 Grade 3	Qualified for production deployment in passenger vehicle ECUs without additional component-level qualification testing, reducing time-to-market for Tier 1 suppliers.
Green Packaging	Lead-free, halide-free, RoHS-compliant TSSOP package - meets global environmental compliance mandates including China RoHS and EU ELV Directive.

Applications

Engine Control Unit (ECU)	Advanced Driver Assistance Systems (ADAS)
Use Scenario: Storing real-time fuel trim coefficients, misfire counters, and diagnostic trouble codes (DTCs) that persist across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile parameter storage element interfaced directly to the ECU's SPI bus; retains data during battery disconnect and supports rapid read-on-boot. Use Value: Enables OBD-II compliance and adaptive learning without external backup capacitors or supercapacitors, reducing BOM cost and PCB area.	Use Scenario: Logging camera calibration offsets, radar fusion metadata, and lane-marking confidence scores for post-crash analysis and OTA update validation. IC Role / Device Role / Timing Role: Secure, tamper-resistant configuration vault for vision/radar processing units; accessed only during initialization or maintenance mode. Use Value: Provides deterministic 100-year retention of safety-critical calibration data, eliminating need for redundant storage or cloud sync in offline operation.
Body Control Module (BCM)	Infotainment Head Unit
Use Scenario: Maintaining user preferences (seat position, mirror angle, lighting profiles) and door/window actuator limits across vehicle lifetime. IC Role / Device Role / Timing Role: Low-power SPI EEPROM operating from 1.8V domain; wakes only during CAN message-triggered configuration load/save sequences. Use Value: Achieves sub-1 µA standby current in sleep mode, extending battery life during prolonged vehicle dormancy (e.g., dealership lot storage).	Use Scenario: Storing audio equalizer presets, Bluetooth pairing history, and display brightness profiles across firmware upgrades and factory resets. IC Role / Device Role / Timing Role: High-reliability data logger co-located with application processor; withstands 1M+ write cycles from frequent UI interactions. Use Value: Eliminates file-system overhead and flash wear leveling complexity by providing byte-addressable, atomic-write EEPROM semantics.

Engine Control Unit (ECU)

Advanced Driver Assistance Systems (ADAS)

Use Scenario: Storing real-time fuel trim coefficients, misfire counters, and diagnostic trouble codes (DTCs) that persist across ignition cycles.

IC Role / Device Role / Timing Role: Nonvolatile parameter storage element interfaced directly to the ECU's SPI bus; retains data during battery disconnect and supports rapid read-on-boot.

Use Value: Enables OBD-II compliance and adaptive learning without external backup capacitors or supercapacitors, reducing BOM cost and PCB area.

Use Scenario: Logging camera calibration offsets, radar fusion metadata, and lane-marking confidence scores for post-crash analysis and OTA update validation.

IC Role / Device Role / Timing Role: Secure, tamper-resistant configuration vault for vision/radar processing units; accessed only during initialization or maintenance mode.

Use Value: Provides deterministic 100-year retention of safety-critical calibration data, eliminating need for redundant storage or cloud sync in offline operation.

Body Control Module (BCM)

Infotainment Head Unit

Use Scenario: Maintaining user preferences (seat position, mirror angle, lighting profiles) and door/window actuator limits across vehicle lifetime.

IC Role / Device Role / Timing Role: Low-power SPI EEPROM operating from 1.8V domain; wakes only during CAN message-triggered configuration load/save sequences.

Use Value: Achieves sub-1 µA standby current in sleep mode, extending battery life during prolonged vehicle dormancy (e.g., dealership lot storage).

Use Scenario: Storing audio equalizer presets, Bluetooth pairing history, and display brightness profiles across firmware upgrades and factory resets.

IC Role / Device Role / Timing Role: High-reliability data logger co-located with application processor; withstands 1M+ write cycles from frequent UI interactions.

Use Value: Eliminates file-system overhead and flash wear leveling complexity by providing byte-addressable, atomic-write EEPROM semantics.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
M95640-DRMN6TP/K	64 Kbit SPI EEPROM, 1.8V–5.5V, AEC-Q100 Grade 2 (−40°C to +105°C), 20 MHz max clock, 5 ms write cycle	Higher speed and wider temp range than AT25640B-XPDGV-T, but lacks HOLD pin and uses different STATUS register layout	Select when faster throughput or extended temperature margin is required, and HOLD functionality is unused in target design.
BR24G64FJ-WE2	64 Kbit I²C EEPROM, 1.7V–5.5V, AEC-Q100 Grade 3, 1 MHz max clock, no WP/HOLD pins, 5 ms write cycle	I²C interface instead of SPI; smaller 8-pin SOP package; no hardware suspend or write-protect pin	Choose for designs already using I²C infrastructure and where SPI bus loading or pin count constraints make I²C preferable despite lower bandwidth.

Compared with M95640-DRMN6TP/K and BR24G64FJ-WE2, the AT25640B-XPDGV-T offers unique combination of SPI Mode 0/3 flexibility, dedicated HOLD pin for bus arbitration, and proven interoperability with automotive-grade microcontrollers - making it optimal for new SPI-based ECU designs prioritizing interface simplicity and functional safety.

Availability

AT25640B-XPDGV-T is available at Aetrix Electronics and suitable for engine control units, ADAS sensor modules, and body control modules requiring stable component supply across automotive production lifecycles.

Supply support for AT25640B-XPDGV-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontroller, analog, FPGA, and memory solutions, serving automotive, industrial, and communications markets with vertically integrated silicon and development tools.

The AT25xxxB family was designed specifically for automotive-grade serial EEPROM applications demanding AEC-Q100 qualification, low-voltage operation, and high reliability in harsh electrical environments - targeting ECU, gateway, and sensor node designs.

FAQ

What is the operating temperature range for the AT25640B-XPDGV-T?

The AT25640B-XPDGV-T is qualified to AEC-Q100 Grade 3 specifications, supporting continuous operation from −40°C to +85°C. This range is validated for cabin and chassis-mounted automotive electronics where full Grade 1 (−40°C to +125°C) is not required. The device maintains full functionality-including 5 MHz SPI operation and 32-byte page writes-across this entire range.

Does the AT25640B-XPDGV-T support both SPI Mode 0 and Mode 3?

Yes, the AT25640B-XPDGV-T explicitly supports SPI Modes 0 (CPOL=0, CPHA=0) and 3 (CPOL=1, CPHA=1). In both modes, data is sampled on the rising edge of SCK and output on the falling edge. The key distinction lies in SCK idle state polarity, allowing compatibility with MCUs that default to either mode without requiring software reconfiguration.

How does hardware write protection work on the AT25640B-XPDGV-T?

Hardware write protection on the AT25640B-XPDGV-T is implemented via the WP pin and STATUS register WPEN bit. When WPEN=1 and WP is driven low, all STATUS register writes (including BP1/BP0 changes) are blocked. If WPEN=0, the WP pin is ignored, enabling STATUS register updates even with WP tied to GND - a feature useful for field-programmable configurations.

What is the maximum write cycle time for the AT25640B-XPDGV-T?

The AT25640B-XPDGV-T guarantees a maximum write cycle time of 5 ms for both byte and page writes. This value is specified under worst-case conditions (VCC = 1.7V, TA = +85°C) and includes internal charge-pump timing. No polling or timeout extension beyond 5 ms is required in production firmware.

Is the AT25640B-XPDGV-T pin-compatible with other packages in the AT25xxxB family?

Yes, the AT25640B-XPDGV-T (8-lead TSSOP) shares identical pinout and function mapping with the SOIC-8 and UDFN-8 variants of the AT25xxxB family, including AT25640B-SSHD-T and AT25640B-MAHD-T. This enables drop-in replacement across form factors without PCB redesign, provided mechanical clearance and thermal constraints are verified for each package type.

AT25640B-XPDGV-T Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 8-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 64Kbit

Memory Organization:: 8K x 8

Memory Interface:: SPI

Clock Frequency:: 5 MHz

Write Cycle Time - Word, Page:: 5ms

Access Time:: -

Voltage - Supply:: 2.5V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: 8-TSSOP

AT25640B-XPDGV-T FAQ

1.How can I place an order for AT25640B-XPDGV-T through Aetrix?

Please submit a Request for Quotation (RFQ) for AT25640B-XPDGV-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT25640B-XPDGV-T reliable?

The price and inventory of AT25640B-XPDGV-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25640B-XPDGV-T is usually 5 days.

3.What payment methods are accepted for AT25640B-XPDGV-T?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25640B-XPDGV-T transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT25640B-XPDGV-T?

AT25640B-XPDGV-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT25640B-XPDGV-T order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT25640B-XPDGV-T?

For technical support, including AT25640B-XPDGV-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25640B-XPDGV-T requirements.

6.How does Aetrix verify that AT25640B-XPDGV-T is sourced from the original manufacturer or authorized distributors?

All AT25640B-XPDGV-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25640B-XPDGV-T meets industry standards.

7.What is the process for return or replacement of AT25640B-XPDGV-T?

All AT25640B-XPDGV-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25640B-XPDGV-T, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT25640B-XPDGV-T part is unused and in its original packaging.

Return procedure for AT25640B-XPDGV-T:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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