Microchip Technology AT25640N-10SI-2.7
- Part No.:
- AT25640N-10SI-2.7
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25640N-10SI-2.7.pdf
- Description:
- IC EEPROM 64KBIT SPI 3MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,437
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25640N-10SI-2.7 from Microchip Technology (formerly Atmel) is a 64 Kbit SPI serial EEPROM organized as 8192 words × 8 bits, operating from 2.7V to 5.5V, supporting 3.0 MHz clock rate at 5V, featuring 32-byte page write, block write protection (1/4, 1/2, or full array), and hardware/software data protection via WP pin and WREN/WRDI instructions. It is used in industrial control systems for firmware parameter storage.
For engineers reviewing the AT25640N-10SI-2.7 datasheet, AT25640N-10SI-2.7 pinout, AT25640N-10SI-2.7 application, or AT25640N-10SI-2.7 equivalent, key selection criteria include low-voltage operation (2.7–5.5 V), SPI Mode 0/3 compatibility, 5 ms typical write cycle time, 1 million endurance cycles, and JEDEC SOIC-8 packaging with verified pin mapping.
Technical Context
The AT25640N-10SI-2.7 implements a synchronous SPI slave interface with separate SI (input) and SO (output) pins, MSB-first data transfer, and chip-select–driven command protocol. It requires WREN before WRITE and supports HOLD pin suspension without sequence reset.
Its status register (8-bit) controls write enable (WEN), ready/busy (RDY), block protection (BP1/BP0), and write-protect enable (WPEN). Block protection is nonvolatile and configurable per Table 4, with hardware write protection active only when WP = low and WPEN = 1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8192 × 8), sufficient for storing calibration tables or device configuration in space-constrained embedded nodes |
| Supply Voltage Range | 2.7 V to 5.5 V - enables direct interfacing with 3.3 V and 5 V microcontrollers without level shifting |
| Max Clock Frequency | 3.0 MHz at VCC = 5.0 V - supports high-throughput parameter updates in real-time control loops |
| Page Write Size | 32 bytes - minimizes write latency versus byte-write EEPROMs; reduces host CPU overhead during bulk writes |
| Write Cycle Time | 5 ms typical - deterministic self-timed erase-and-write eliminates need for external timing control |
| Endurance | 1 million write cycles - suitable for logging applications with frequent updates (e.g., energy metering) |
| Data Retention | 100 years - ensures long-term reliability in unattended infrastructure equipment |
Pinout & Package
AT25640N-10SI-2.7 is supplied in an 8-lead JEDEC SOIC package (package code 8S1), 0.150" wide body, with standard gull-wing leads and 1.27 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable; must be held low for entire instruction sequence (op-code + address + data) |
| SCK | Serial Clock | Input-only master-generated clock; defines timing for SI sampling and SO output edges |
| SI | Serial Data Input | Command, address, and write-data input path; sampled on SCK rising edge in Mode 0 |
| SO | Serial Data Output | Read-data output path; driven on SCK falling edge in Mode 0; high-impedance when CS high or during HOLD |
| WP | Write Protect | Hardware lock for status register and protected memory blocks when WPEN = 1 and WP = low |
| HOLD | Communication Suspend | Pauses ongoing read/write without resetting internal address counter; requires SCK low to assert |
| GND | Ground Reference | Return path for all digital I/O and supply current; must be low-impedance for noise immunity |
| VCC | Power Supply | Single 2.7–5.5 V supply; decoupling capacitor (0.1 µF) required within 10 mm of VCC/GND pins |
Key Features
| Feature | Design Value |
|---|---|
| SPI Mode 0 and 3 support | Interoperates with legacy 68HC11 and modern ARM Cortex-M SPI peripherals without mode reconfiguration |
| Block write protection (1/4, 1/2, full) | Enables secure storage of bootloader code in protected region while allowing runtime parameter updates in unprotected region |
| Self-timed 5 ms write cycle | Eliminates need for polling delay loops or external timers - simplifies firmware and improves determinism |
| HOLD pin functionality | Allows microcontroller to service higher-priority interrupts mid-transaction without losing EEPROM state or address pointer |
| 1.8 V–5.5 V dual-voltage variants | Same footprint and command set across voltage grades - enables single PCB design for 1.8 V and 3.3 V system variants |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
Use Scenario: Storing temperature-compensation coefficients and sensor offset values during factory calibration of pressure transducers. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with guaranteed 100-year retention and 1M endurance under repeated field recalibration. Use Value: Eliminates need for external backup batteries or supercapacitors; supports recalibration every 6 months over 15+ year product life. | Use Scenario: Holding user-selected therapy parameters (e.g., infusion rate, alarm thresholds) in portable insulin pumps. IC Role / Device Role / Timing Role: Secure, low-power configuration memory accessed via SPI during boot and mode changes. Use Value: WP pin + BP bits prevent accidental overwrite of safety-critical settings; 2.7 V operation ensures function during brownout conditions. |
| Automotive Body Control Module | Smart Energy Meter Firmware |
Use Scenario: Saving seat/mirror position presets and lighting profiles in 12 V automotive systems with local 3.3 V regulation. IC Role / Device Role / Timing Role: SPI EEPROM interfaced directly to MCU GPIOs; withstands -40°C to +85°C industrial temp range. Use Value: JEDEC SOIC-8 package fits tight board spaces; 32-byte page write reduces CAN bus interrupt latency during profile saves. | Use Scenario: Storing tariff schedules, demand-response commands, and metering history logs in ANSI C12.22-compliant smart meters. IC Role / Device Role / Timing Role: High-reliability data logger with atomic 32-byte writes and RDY/BUSY flag for power-fail-safe logging. Use Value: 5 ms write time enables logging of 1-second interval data without missing samples during mains dropout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M95640-DW DW | STMicroelectronics 64 Kbit SPI EEPROM; identical 8-lead SOIC package, 2.5–5.5 V supply, 20 MHz max clock, but uses different status register layout and lacks HOLD pin | Supports faster clock rates but requires firmware adaptation for status bit interpretation and no suspend capability | Select when higher throughput is critical and HOLD functionality is unused |
| CAT25640VI-GT3 | onsemi 64 Kbit SPI EEPROM; same 8-lead SOIC, 1.8–5.5 V, 10 MHz max clock, includes HOLD and WP, but specifies 10 ms max write cycle vs. 5 ms typical for AT25640N-10SI-2.7 | Compatible pinout and command set; longer worst-case write time may impact real-time logging deadlines | Select when extended voltage range (1.8 V) is required and 10 ms write tolerance is acceptable |
Compared with M95640-DW and CAT25640VI-GT3, AT25640N-10SI-2.7 offers the shortest typical write cycle (5 ms), native HOLD support for interruptible transactions, and proven interoperability with legacy 68HC11-based designs - making it optimal for deterministic, low-latency embedded parameter storage.
Availability
AT25640N-10SI-2.7 is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, automotive body control modules, and smart energy meter firmware requiring stable component supply across extended temperature ranges and multi-year production cycles.
Supply support for AT25640N-10SI-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions, with a focus on reliability and long-term product support.
The AT25640N-10SI-2.7 belongs to Microchip's legacy AT25 SPI EEPROM family, designed for robust, low-power, pin-efficient nonvolatile storage in industrial, automotive, and medical applications where data integrity and endurance are critical.
FAQ
What is the maximum clock frequency supported by the AT25640N-10SI-2.7?
The AT25640N-10SI-2.7 supports up to 3.0 MHz at VCC = 5.0 V, 2.1 MHz at VCC = 2.7–5.5 V, and 0.5 MHz at VCC = 1.8–5.5 V. These values are specified in the AC Characteristics table under fSCK. The actual usable frequency depends on VCC level and ambient temperature, with derating required outside the 2.7–5.5 V range. AT25640N-10SI-2.7 does not support frequencies above 3.0 MHz even at 5 V.
Does the AT25640N-10SI-2.7 support both SPI Mode 0 and Mode 3?
Yes, the AT25640N-10SI-2.7 explicitly supports SPI Modes 0 (CPOL = 0, CPHA = 0) and 3 (CPOL = 1, CPHA = 1), as stated in its Features section. This dual-mode capability allows seamless integration with diverse microcontrollers including legacy 68HC11 (Mode 0) and certain ARM-based SoCs (Mode 3). AT25640N-10SI-2.7 does not support Mode 1 or Mode 2.
How does the HOLD pin function during an active read or write sequence on the AT25640N-10SI-2.7?
The HOLD pin on the AT25640N-10SI-2.7 suspends serial communication without resetting the internal address counter or command state. To activate HOLD, the pin must be driven low while SCK is low; SO enters high-impedance, and SI inputs are ignored. Resuming requires bringing HOLD high while SCK remains low. AT25640N-10SI-2.7 retains full context and continues from the exact bit position upon resume.
What protection mechanisms prevent unintended writes to the AT25640N-10SI-2.7?
AT25640N-10SI-2.7 employs three layered protections: (1) software-based WREN/WRDI instructions to gate all write operations, (2) status-register-controlled block protection (BP1/BP0) enabling 1/4, 1/2, or full-array lockdown, and (3) hardware WP pin that disables status register and protected memory writes when WP = low and WPEN = 1. All three must be satisfied for a write to succeed.
Is the AT25640N-10SI-2.7 qualified for automotive applications?
The AT25640N-10SI-2.7 is rated for industrial temperature range (−40°C to +85°C) and is not AEC-Q100 qualified. While the datasheet notes "Automotive Grade Devices Available" for the AT25xxx family, that refers to specific automotive-grade variants (e.g., AT25640AN-10SI-2.7 with suffix 'A'), not the standard AT25640N-10SI-2.7. For automotive use, AT25640N-10SI-2.7 requires qualification testing per customer requirements.
AT25640N-10SI-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 3 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25640N-10SI-2.7 FAQ
1.How can I place an order for AT25640N-10SI-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25640N-10SI-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25640N-10SI-2.7 reliable?
The price and inventory of AT25640N-10SI-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25640N-10SI-2.7 is usually 5 days.
3.What payment methods are accepted for AT25640N-10SI-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25640N-10SI-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25640N-10SI-2.7?
AT25640N-10SI-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25640N-10SI-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25640N-10SI-2.7?
For technical support, including AT25640N-10SI-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25640N-10SI-2.7 requirements.
6.How does Aetrix verify that AT25640N-10SI-2.7 is sourced from the original manufacturer or authorized distributors?
All AT25640N-10SI-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25640N-10SI-2.7 meets industry standards.
7.What is the process for return or replacement of AT25640N-10SI-2.7?
All AT25640N-10SI-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with AT25640N-10SI-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25640N-10SI-2.7 part is unused and in its original packaging.
Return procedure for AT25640N-10SI-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25640N-10SI-2.7 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
