Renesas AT25DF041B-UUNHR-T
- Part No.:
- AT25DF041B-UUNHR-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-XFBGA, WLCSP
- Datasheet:
-
AT25DF041B-UUNHR-T.pdf
- Description:
- IC FLASH 4MBIT SPI 85MHZ 8WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:3,312
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25DF041B-UUNHR-T from Renesas Electronics is a 4-Mbit serial SPI Flash memory IC designed for code shadowing and embedded data storage in resource-constrained systems. It operates from 1.65 V to 3.6 V across –40 °C to +85 °C, supports Dual-I/O read mode at up to 104 MHz, delivers 6 ns clock-to-output timing, and features uniform 4-kByte/32-kByte/64-kByte block erase plus 256-byte page erase.
For engineers reviewing the AT25DF041B-UUNHR-T datasheet, AT25DF041B-UUNHR-T pinout, AT25DF041B-UUNHR-T application, or AT25DF041B-UUNHR-T equivalent, this device serves as a drop-in upgrade path for legacy SPI Flash in industrial controllers, IoT edge nodes, and firmware-boot MCU platforms requiring fast dual-I/O reads, low-power deep-sleep modes, and flexible sector protection.
Technical Context
The AT25DF041B-UUNHR-T implements a standard SPI interface compliant with Modes 0 and 3, using rising-edge input sampling and falling-edge output latching. Its internal architecture integrates a 4-Mbit NOR Flash array with dedicated SRAM data buffer, Y/X decoders, and hardware-controlled protection logic tied to WP and HOLD pins.
Dual-I/O operation repurposes SI (I/O0) and SO (I/O1) as concurrent output lines during Dual-Output Read commands, doubling data throughput versus standard single-I/O reads. Erase granularity-256-byte pages, 4/32/64-kByte blocks, and full-chip-enables efficient co-location of firmware code and runtime configuration data without cross-contamination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 Mbit (512 KByte) NOR Flash with byte-addressable random access |
| Supply Voltage | 1.65 V–3.6 V - enables direct interfacing with 1.8 V and 3.3 V MCUs without level shifters |
| Max Clock Frequency | 104 MHz - supports high-speed boot code fetch and firmware updates |
| Read Latency | 6 ns clock-to-output (tV) - minimizes instruction fetch stalls in real-time execution |
| Erase Granularity | 256-byte page, 4/32/64-kByte uniform blocks - allows independent update of bootloader, app, and config sectors |
| Endurance & Retention | 100,000 P/E cycles / 20 years data retention - validated for long-life industrial deployment |
| Power Consumption | 200 nA ultra-deep power-down current - extends battery life in always-on sensor nodes |
Pinout & Package
AT25DF041B-UUNHR-T is packaged in an 8-pad Ultra Thin DFN (2 × 3 × 0.6 mm) with wettable flank leads, RoHS-compliant and halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must transition low-to-high to complete any command sequence |
| SCK | Serial Clock | Master-generated clock; rising edge latches input (SI), falling edge clocks output (SO/I/O0) |
| SI (I/O0) | Serial Input / Dual-I/O Data 0 | Command/address/data input; becomes output (I/O0) during Dual-Output Read for parallel bit streaming |
| SO (I/O1) | Serial Output / Dual-I/O Data 1 | Data output in standard mode; remains active output (I/O1) during Dual-Output Read with SI |
| WP | Write Protect | Hardware lock control; low assertion enables sector-level write/erase blocking independent of software commands |
| HOLD | Hold Input | Pauses ongoing SPI transfers without deselecting device or interrupting internal program/erase cycles |
| VCC | Power Supply | Single 1.65–3.6 V rail powers all logic and Flash operations - no auxiliary voltage required |
| GND | Ground Reference | System ground return path; critical for noise immunity in high-frequency SPI signaling |
Key Features
| Feature | Design Value |
|---|---|
| Dual-I/O Read Mode | Simultaneous 2-bit output on SI/I/O0 and SO/I/O1 doubles effective read bandwidth over standard SPI |
| Flexible Erase Architecture | Four distinct erase granularities (page/block/chip) eliminate wasted space when mixing code and data in same device |
| 128-Byte OTP Security Register | 64-byte factory-unique ID + 64-byte user-programmable space for secure key storage or device serialization |
| Hardware Write Protection | WP pin provides tamper-resistant, non-volatile sector locking - persists through power cycles and resets |
| Ultra-Low Power Modes | 200 nA ultra-deep power-down and 5 µA deep power-down enable multi-year battery operation in sleep states |
Applications
| Industrial PLC Firmware Storage | IoT Edge Node Configuration |
|---|---|
|
Use Scenario: Storing boot firmware, safety-critical control logic, and field-upgradable application binaries in programmable logic controllers. IC Role / Device Role / Timing Role: Non-volatile code storage with deterministic 6 ns tV latency enabling sub-microsecond instruction fetch during real-time scan cycles. Use Value: Uniform 4-kByte block erase allows safe in-field updates of individual function modules without corrupting runtime OS or I/O drivers. |
Use Scenario: Holding calibrated sensor offsets, network credentials, and OTA update staging buffers in battery-powered environmental monitors. IC Role / Device Role / Timing Role: Low-power data logger memory supporting frequent small writes (256-byte pages) and infrequent bulk reconfiguration. Use Value: 200 nA ultra-deep power-down current extends 10-year battery life while retaining full firmware integrity between wake events. |
| Medical Diagnostic Bootloader | Automotive Body Control Module |
|
Use Scenario: Securely storing certified bootloader images and cryptographic keys in portable ultrasound or ECG devices. IC Role / Device Role / Timing Role: Trusted boot source with 128-byte OTP register holding factory-programmed unique identifiers and encrypted key material. Use Value: Hardware WP pin ensures bootloader region remains immutable during field service or firmware recovery procedures. |
Use Scenario: Hosting lighting control algorithms, seat position profiles, and CAN message lookup tables in automotive interior ECUs. IC Role / Device Role / Timing Role: Dual-I/O read mode accelerates CAN message table lookups during 100+ kHz bus arbitration cycles. Use Value: 104 MHz max clock frequency and 6 ns tV reduce CPU wait states, improving real-time responsiveness under peak bus load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q40EW | Same 4-Mbit density, 1.7–3.6 V supply, but only supports single-I/O and Quad-I/O (no Dual-I/O); 80 MHz max clock | Lacks Dual-I/O read mode - lower throughput in bandwidth-sensitive boot scenarios | Choose when Quad-I/O compatibility or lower cost outweighs need for 104 MHz Dual-I/O performance |
| Micron MT25QL04A | 4-Mbit, 1.7–3.6 V, supports Dual-I/O and Quad-I/O; 133 MHz max clock but requires 1.8 V minimum | Higher speed but incompatible with 1.65 V systems; deeper power-down current is 2 µA (vs. 200 nA) | Prefer for 1.8 V+ designs needing faster read rates; avoid where ultra-low sleep current is mandatory |
Compared with W25Q40EW and MT25QL04A, the AT25DF041B-UUNHR-T uniquely balances 104 MHz Dual-I/O throughput, 1.65 V operation, and 200 nA ultra-deep power-down - making it optimal for battery-backed industrial and medical edge devices requiring both speed and longevity.
Availability
AT25DF041B-UUNHR-T is available at Aetrix Electronics and suitable for industrial PLC firmware storage, IoT edge node configuration, medical diagnostic bootloader, and automotive body control module applications requiring stable component supply and long-term lifecycle support.
Supply support for AT25DF041B-UUNHR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog, power, and memory solutions for automotive, industrial, infrastructure, and IoT markets.
The AT25DF041B belongs to Renesas' serial Flash memory product line, engineered specifically for reliable, low-voltage, high-speed code and data storage in space- and power-constrained embedded systems.
FAQ
What is the operating temperature range for the AT25DF041B-UUNHR-T?
The AT25DF041B-UUNHR-T is rated for the full industrial temperature range of –40 °C to +85 °C. This specification is validated per Renesas DS-AT25DF041B-040 Rev. H, with guaranteed performance including 100,000 program/erase cycles and 20-year data retention within this range. The device also supports extended operation to +125 °C with derated endurance (20,000 cycles).
Does the AT25DF041B-UUNHR-T support Quad-I/O mode?
No, the AT25DF041B-UUNHR-T does not support Quad-I/O mode. It supports SPI Modes 0 and 3, standard single-I/O read/write, and Dual-I/O read (using SI and SO as concurrent outputs). Quad-I/O functionality is absent per the official Renesas datasheet DS-AT25DF041B-040, which explicitly lists only Dual-I/O capability in its features and command set.
How is hardware write protection implemented on the AT25DF041B-UUNHR-T?
Hardware write protection on the AT25DF041B-UUNHR-T is controlled via the WP (Write Protect) pin, which enables non-volatile sector locking independent of software commands. When WP is asserted low, protected sectors remain immune to program and erase operations-even if software write-enable commands are issued. This behavior is defined in Section 9.7 of the datasheet and complements software-based protection registers.
What package type is used for the AT25DF041B-UUNHR-T?
The AT25DF041B-UUNHR-T uses an 8-pad Ultra Thin DFN package measuring 2 mm × 3 mm × 0.6 mm, with wettable flank leads for enhanced solder joint inspection. This package variant is confirmed in Renesas' Ordering Information (Section 16) and Packaging Information (Section 17.2) of DS-AT25DF041B-040 Rev. H.
Can the AT25DF041B-UUNHR-T be used in 1.65 V systems?
Yes, the AT25DF041B-UUNHR-T is fully specified to operate down to 1.65 V across –40 °C to +85 °C, as stated in its primary feature list and DC characteristics tables (Tables 15 and 17). This enables direct integration with 1.8 V I/O domains and low-voltage microcontrollers without level-shifting circuitry.
AT25DF041B-UUNHR-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-XFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 85 MHz
- Write Cycle Time - Word, Page:
- 8µs, 2.5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WLCSP (1.63x1.58)
AT25DF041B-UUNHR-T FAQ
1.How can I place an order for AT25DF041B-UUNHR-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25DF041B-UUNHR-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25DF041B-UUNHR-T reliable?
The price and inventory of AT25DF041B-UUNHR-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25DF041B-UUNHR-T is usually 5 days.
3.What payment methods are accepted for AT25DF041B-UUNHR-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25DF041B-UUNHR-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25DF041B-UUNHR-T?
AT25DF041B-UUNHR-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25DF041B-UUNHR-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25DF041B-UUNHR-T?
For technical support, including AT25DF041B-UUNHR-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25DF041B-UUNHR-T requirements.
6.How does Aetrix verify that AT25DF041B-UUNHR-T is sourced from the original manufacturer or authorized distributors?
All AT25DF041B-UUNHR-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25DF041B-UUNHR-T meets industry standards.
7.What is the process for return or replacement of AT25DF041B-UUNHR-T?
All AT25DF041B-UUNHR-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25DF041B-UUNHR-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25DF041B-UUNHR-T part is unused and in its original packaging.
Return procedure for AT25DF041B-UUNHR-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25DF041B-UUNHR-T Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

.jpg)