Renesas AT25DF161-SH-B

Overview

AT25DF161-SH-B from Adesto Technologies (now part of Dialog Semiconductor, acquired by Renesas) is a 16-Mbit serial SPI Flash memory IC designed for code shadowing and mixed code/data storage in embedded systems. It operates from a single 2.7V–3.6V supply, supports RapidS at 100 MHz and standard SPI at 85 MHz, delivers ≤5 ns clock-to-output delay, and features uniform 4/32/64-Kbyte block erase plus full chip erase.

For engineers reviewing the AT25DF161-SH-B datasheet, AT25DF161-SH-B pinout, AT25DF161-SH-B application, or AT25DF161-SH-B equivalent, key selection criteria include its dual-input/dual-output read/write capability, sector lockdown for permanent read-only protection, 128-byte OTP security register, industrial temperature range (–40°C to +85°C), and RoHS-compliant 8-lead SOIC package.

Technical Context

The AT25DF161-SH-B implements a flexible erase architecture with four physical erase granularities-4-Kbyte, 32-Kbyte, 64-Kbyte blocks, and full chip-enabling efficient partitioning of code and data segments without wasted space. Its memory array comprises 32 uniform 64-Kbyte sectors, each individually protectable via software or hardware (WP pin).

It supports SPI Modes 0 and 3, includes dual-input programming (SOI/SI) and dual-output reading (SO/SIO), and integrates intelligent program/erase suspend/resume, automatic failure detection (EPE flag), and deep power-down mode drawing only 5 µA typical current. The device uses a dedicated SRAM data buffer and internal address counter for seamless sequential access.

Key Specifications

Pinout & Package

AT25DF161-SH-B is packaged in an industry-standard 8-lead SOIC (208-mil wide), pin-compatible with JEDEC MS-012AC. All pins support 3.3V logic levels and are CMOS-compatible.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial Flash memory applications.

Compared with W25Q16JV-IQ and MX25L1606E, the AT25DF161-SH-B uniquely combines RapidS performance, dual I/O acceleration, hardware-based sector lockdown, and a dedicated OTP register-making it optimal for secure, upgradable embedded firmware where code integrity and field update flexibility are critical.

Availability

AT25DF161-SH-B is available at Aetrix Electronics and suitable for industrial control firmware storage, automotive infotainment code shadowing, and medical device data logging requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for AT25DF161-SH-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Adesto Technologies specialized in low-power, high-reliability non-volatile memory solutions before its acquisition by Dialog Semiconductor in 2020, now part of Renesas Electronics.

The AT25DF161-SH-B belongs to Adesto's DataFlash® family, engineered for mixed code-and-data applications demanding fast, flexible erase granularity, robust security features, and industrial-grade reliability in resource-constrained embedded systems.

FAQ

What is the maximum clock frequency supported by AT25DF161-SH-B in RapidS mode?

The AT25DF161-SH-B supports up to 100 MHz in RapidS mode, enabling high-speed sequential reads with minimal latency. This exceeds standard SPI limits and is validated for use with the 1Bh opcode. Operation above 85 MHz requires adherence to RapidS protocol timing constraints, including dummy byte insertion and proper signal integrity layout. The 5 ns clock-to-output (tV) specification ensures deterministic timing at this rate.

Does AT25DF161-SH-B support hardware write protection via the WP pin?

Yes, AT25DF161-SH-B provides hardware-controlled write protection through the WP pin, which locks protected sectors when asserted low. This complements software-based sector protection and global protect/unprotect commands. The WP pin is internally pulled high, so it may be left floating if unused-but external connection to VCC is recommended for noise immunity. Hardware locking remains active even after power cycles.

Can AT25DF161-SH-B be used for secure key storage?

Yes, AT25DF161-SH-B includes a 128-byte One-Time Programmable (OTP) Security Register specifically designed for secure key storage, device serialization, or Electronic Serial Number (ESN) retention. Once programmed, OTP contents cannot be erased or rewritten, providing tamper-resistant storage for cryptographic keys, calibration data, or licensing tokens essential in secure boot and firmware authentication workflows.

What erase block sizes does AT25DF161-SH-B support?

AT25DF161-SH-B supports four uniform erase granularities: 4-Kbyte, 32-Kbyte, and 64-Kbyte blocks, plus full chip erase. Each 64-Kbyte sector contains eight 4-Kbyte sub-blocks and two 32-Kbyte sub-blocks. This hierarchical structure allows precise firmware patching (e.g., updating a single driver module) without erasing unrelated code or configuration data-reducing wear and improving system update efficiency.

Is AT25DF161-SH-B compatible with standard SPI Mode 0 and Mode 3?

Yes, AT25DF161-SH-B is fully compatible with SPI Modes 0 and 3, defined by SCK polarity and phase. In both modes, data is latched on the rising edge of SCK and output on the falling edge. Mode 0 uses idle-low SCK; Mode 3 uses idle-high SCK. No configuration register setting is required-the device automatically interprets the timing, ensuring plug-and-play integration with common microcontrollers including ARM Cortex-M, PIC, and ESP32 families.