Renesas AT25DF161-SH-T
- Part No.:
- AT25DF161-SH-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
AT25DF161-SH-T.pdf
- Description:
- IC FLASH 16MBIT SPI 100MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT25DF161-SH-T from Adesto Technologies (now part of Dialog Semiconductor) is a 16-Mbit serial SPI Flash memory IC designed for code shadowing and mixed code/data storage in embedded systems. It operates from a single 2.7V–3.6V supply, supports RapidS (100 MHz) and standard SPI (85 MHz) modes, features 4/32/64-Kbyte uniform erase blocks, and delivers ≤5 ns clock-to-output delay - enabling high-speed boot and firmware update in resource-constrained industrial and consumer devices.
For engineers reviewing the AT25DF161-SH-T datasheet, AT25DF161-SH-T pinout, AT25DF161-SH-T application, or AT25DF161-SH-T equivalent, key selection criteria include its dual-input/dual-output read/write capability, sector lockdown security, 128-byte OTP register, 100,000 program/erase endurance, and support for industrial temperature range (−40°C to +85°C) with RoHS-compliant SOIC and DFN packaging.
Technical Context
The AT25DF161-SH-T implements a flexible SPI interface supporting Modes 0 and 3, with dual-input programming (SOI/SI) and dual-output reading (SO/SIO) to double effective data throughput. Its memory architecture divides the 16-Mbit array into 32 uniform 64-Kbyte sectors, each individually protectable via hardware (WP pin) or software commands.
It integrates dedicated control logic for sector lockdown (permanent read-only), global protect/unprotect, and automatic program/erase failure detection. The device uses an internal SRAM data buffer and intelligent programming algorithm to verify byte-level write integrity and report errors via the EPE bit in the Status Register.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 16 Mbit (2 Mbytes) - sufficient for full bootloader + application firmware in compact MCU systems. |
| Supply Voltage | 2.7V–3.6V - compatible with 3.3V logic rails without level-shifting or auxiliary supplies. |
| Max Read Frequency | 100 MHz (RapidS mode) - enables sub-200 ns access per byte, critical for fast code execution from flash. |
| Page Program Time | 1.0 ms typical (256 bytes) - reduces firmware update latency in field-deployed devices. |
| Erase Granularity | 4-Kbyte / 32-Kbyte / 64-Kbyte blocks + full chip - allows precise over-the-air patching without erasing entire application. |
| Endurance & Retention | 100,000 cycles / 20 years - meets long-life requirements for industrial controllers and medical firmware storage. |
| Deep Power-Down Current | 5 µA typical - extends battery life in always-on IoT edge nodes during idle periods. |
Pinout & Package
AT25DF161-SH-T is available in 8-lead SOIC (208-mil wide) and 8-pad Ultra Thin DFN (5 × 6 × 0.6 mm) packages. Both variants share identical pin functions and ordering suffix "-SH-T" denotes the SOIC package.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select input | Active-low enable; must transition low-to-high to terminate operations and return SO to high-Z state. |
| SCK | Serial clock input | Controls data timing; rising edge latches SI/SIO, falling edge clocks out SO/SIO - supports up to 100 MHz. |
| SI (SIO) | Serial input / dual-output data line | Primary command/address/data input; becomes SIO output during Dual-Output Read for 2-bit-per-cycle transfer. |
| SO (SOI) | Serial output / dual-input data line | Primary data output; becomes SOI input during Dual-Input Program to accept parallel bit pairs with SI. |
| WP | Hardware write-protect input | Low-active pin that locks protected sectors; internally pulled high - can be left floating if unused. |
| HOLD | Communication pause input | Halts ongoing SPI transfers without deselecting CS; requires SCK low and CS active to initiate hold. |
| VCC | Power supply | 2.7V–3.6V main supply; powers all internal logic, memory array, and I/O buffers. |
| GND | Ground reference | System ground connection; required for stable operation and noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-Output Read Array (3Bh) | Delivers 2 bits per SCK cycle - doubles read bandwidth vs. standard SPI, accelerating boot time by ~40% at same clock rate. |
| Sector Lockdown (33h) | Makes any combination of 64-Kbyte sectors permanently read-only - prevents tampering with secure boot code or cryptographic keys. |
| 128-byte OTP Security Register | Stores immutable device-specific data (e.g., ESN, encryption keys) - survives full chip erase and cannot be reprogrammed. |
| Flexible Erase Architecture | Supports 4-Kbyte block erase - enables fine-grained firmware patching without disturbing adjacent code or configuration data. |
| Program/Erase Suspend & Resume | Allows interrupting long erase cycles to service high-priority reads - essential for real-time systems with concurrent storage access. |
Applications
| Industrial PLC Firmware Storage | Medical Device Bootloader |
|---|---|
Use Scenario: Storing and updating ladder logic firmware in programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Non-volatile code storage with rapid read access for deterministic boot and hot-swappable module updates. Use Value: 4-Kbyte erase granularity enables patching individual function blocks without full reflash; 100,000-cycle endurance ensures >10-year field life under frequent update cycles. |
Use Scenario: Securing boot firmware and calibration data in portable diagnostic equipment requiring FDA-compliant data integrity. IC Role / Device Role / Timing Role: Trusted code repository with permanent lockdown of bootloader and cryptographic keys to prevent unauthorized modification. Use Value: Sector lockdown (33h) and OTP register (9Bh/77h) provide hardware-enforced immutability - meeting IEC 62304 software safety requirements. |
| Smart Home Gateway OTA Updates | Automotive Infotainment System |
Use Scenario: Hosting application firmware and UI assets in Wi-Fi/Zigbee gateways performing remote over-the-air (OTA) updates. IC Role / Device Role / Timing Role: Dual-input programming (A2h) accelerates firmware download; deep power-down (B9h) minimizes standby current. Use Value: 1.0 ms page program time and 5 µA deep power-down reduce update duration and extend battery backup runtime during brownout events. |
Use Scenario: Storing infotainment OS kernel, voice recognition models, and map data in automotive head units with strict thermal and reliability constraints. IC Role / Device Role / Timing Role: High-speed RapidS read (100 MHz) enables <200 ms boot time; industrial temp rating (−40°C to +85°C) ensures operation across cabin extremes. Use Value: ≤5 ns tV (clock-to-output) and 85 MHz SPI compatibility guarantee deterministic timing margins for ASIL-B compliant boot sequences. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q16JV-IQ | 16-Mbit, 1.65–3.6V supply, 133 MHz max read, no dual-input programming or sector lockdown. | Lacks hardware-based permanent sector lock; relies on software protection only. | Choose when higher speed and broader voltage range are prioritized over tamper-proof lockdown. |
| Macronix MX25L1606E-M2I | 16-Mbit, 2.7–3.6V, 80 MHz max read, supports standard SPI only (no RapidS or dual I/O). | No dual-output read or OTP register; simpler command set but lower bandwidth. | Choose for cost-sensitive designs where 100 MHz RapidS and dual I/O are not required. |
Compared with W25Q16JV-IQ and MX25L1606E-M2I, the AT25DF161-SH-T uniquely combines RapidS performance, dual-input/dual-output capability, and hardware-enforced sector lockdown - making it optimal for secure, high-throughput embedded firmware storage where code integrity and update efficiency are jointly critical.
Availability
AT25DF161-SH-T is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics, smart home gateways, automotive infotainment, and portable instrumentation requiring stable component supply across extended product lifecycles.
Supply support for AT25DF161-SH-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Adesto Technologies, acquired by Dialog Semiconductor in 2020, specialized in ultra-low-power, high-performance non-volatile memory and analog solutions for IoT and embedded applications.
The AT25DF161-SH-T belongs to Adesto's DataFlash® family - engineered specifically for mixed code-and-data storage in space-constrained, power-sensitive systems requiring fast read/write, robust security, and industrial-grade reliability.
FAQ
What is the maximum clock frequency supported by AT25DF161-SH-T in RapidS mode?
The AT25DF161-SH-T supports up to 100 MHz in RapidS mode using the 1Bh opcode, enabling high-speed sequential reads with ≤5 ns clock-to-output delay. This exceeds standard SPI limits and is validated for reliable operation across the full industrial temperature range (−40°C to +85°C). The AT25DF161-SH-T achieves this via optimized internal timing and dual-output capability, not just higher clock tolerance.
Does AT25DF161-SH-T support true pin-compatible replacement for legacy AT25DF081 devices?
No - while AT25DF161-SH-T shares the same pinout and command set as AT25DF081, it doubles the density to 16 Mbit and adds RapidS support, dual-input programming, and enhanced security features. Hardware design remains compatible, but firmware must validate address range (up to 1FFFFFh) and enable new opcodes (e.g., 3Bh, A2h); the AT25DF161-SH-T is not a drop-in replacement without software review.
How does the sector lockdown feature work in AT25DF161-SH-T?
The AT25DF161-SH-T implements permanent sector lockdown via the 33h command, which irreversibly sets lockdown bits in non-volatile registers for any combination of its 32 × 64-Kbyte sectors. Once locked, those sectors become read-only for all subsequent program/erase commands - even after power cycles or reset. This protects boot code and keys from malicious overwrite, and the AT25DF161-SH-T provides freeze (34h) and read-back (35h) commands to verify lockdown state.
Can AT25DF161-SH-T operate reliably at 2.7V minimum supply voltage?
Yes - the AT25DF161-SH-T is fully specified for operation across 2.7V–3.6V, including all read, program, and erase functions at 2.7V. At this minimum voltage, typical active read current is 5 mA (at 20 MHz), and deep power-down current remains 5 µA. All timing parameters, including 100 MHz RapidS read, are guaranteed down to 2.7V per the official datasheet (3687C–DFLASH–7/09), confirming robust low-voltage operation for battery-backed systems.
What package options are available for AT25DF161-SH-T?
The AT25DF161-SH-T is offered exclusively in 8-lead SOIC (208-mil wide) packaging, indicated by the "-SH-T" suffix. While the underlying AT25DF161 die supports both SOIC and 8-pad DFN (5 × 6 × 0.6 mm), the "-SH-T" variant is SOIC-only. The DFN version carries a different suffix (e.g., "-MHN-T"). Pinout, functionality, and electrical specs are identical between packages - only mechanical footprint and thermal characteristics differ.
AT25DF161-SH-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 16Mbit
- Memory Organization:
- 2M x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 100 MHz
- Write Cycle Time - Word, Page:
- 7µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25DF161-SH-T FAQ
1.How can I place an order for AT25DF161-SH-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25DF161-SH-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25DF161-SH-T reliable?
The price and inventory of AT25DF161-SH-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25DF161-SH-T is usually 5 days.
3.What payment methods are accepted for AT25DF161-SH-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25DF161-SH-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25DF161-SH-T?
AT25DF161-SH-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25DF161-SH-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25DF161-SH-T?
For technical support, including AT25DF161-SH-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25DF161-SH-T requirements.
6.How does Aetrix verify that AT25DF161-SH-T is sourced from the original manufacturer or authorized distributors?
All AT25DF161-SH-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25DF161-SH-T meets industry standards.
7.What is the process for return or replacement of AT25DF161-SH-T?
All AT25DF161-SH-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25DF161-SH-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25DF161-SH-T part is unused and in its original packaging.
Return procedure for AT25DF161-SH-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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