Renesas AT25PE20-SSHN-B
- Part No.:
- AT25PE20-SSHN-B
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT25PE20-SSHN-B.pdf
- Description:
- IC FLASH 2MBIT SPI 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,482
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Product details
Overview
AT25PE20-SSHN-B from Adesto Technologies is a 2-Mbit serial Flash memory with SPI interface, 1.65V–3.6V single-supply operation, RapidS™ high-speed mode (up to 85 MHz), 256/264-byte configurable page size, and integrated 256/264-byte SRAM buffer. It supports byte/page program, page/block/sector/chip erase, and continuous read across page boundaries - ideal for firmware storage and data logging in space-constrained industrial controllers.
For engineers reviewing the AT25PE20-SSHN-B datasheet, AT25PE20-SSHN-B pinout, AT25PE20-SSHN-B application, or AT25PE20-SSHN-B equivalent, key selection criteria include its ultra-low deep power-down current (300 nA), hardware write protection (WP pin), reset functionality, JEDEC-compliant ID read, and support for E²PROM emulation via read-modify-write.
Technical Context
The AT25PE20-SSHN-B implements a sequential-access DataFlash-L® architecture with dual-level memory organization: 1,024 pages of main array (256 or 264 bytes each) plus one dedicated SRAM buffer of matching size. Its SPI interface supports modes 0 and 3, with four distinct continuous read opcodes (0Bh, 03h, 01h, E8h) optimized for speed, low power, or legacy compatibility.
All erase and program operations are self-timed and internally managed; the device uses intelligent algorithms to detect programming/erase failures via the EPE bit in the Status Register. The 128-byte Security Register contains a factory-programmed unique identifier, and sector protection is enforced both by software register and hardware WP pin assertion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory density | 2,162,688 bits (2-Mbit), organized as 1,024 pages × 256/264 bytes |
| Supply voltage | 1.65V–3.6V single supply - enables direct interfacing with 1.8V/2.5V/3.3V logic without level shifters |
| Max clock frequency | 85 MHz (RapidS™ mode) - supports high-throughput firmware updates and streaming audio playback |
| Power-down current | 300 nA typical (Ultra-Deep Power-Down) - extends battery life in always-on sensor nodes |
| Page erase time | tEP ≤ 25 ms - enables fast field firmware patching without full chip reprogramming |
| Data retention | 20 years at 85°C - meets long-lifecycle requirements for industrial automation and medical devices |
| Endurance | 100,000 program/erase cycles per page - supports frequent data logging in telemetry applications |
Pinout & Package
AT25PE20-SSHN-B is supplied in an 8-lead SOIC package (0.208" wide), RoHS-compliant and halogen-free. Pin functions are electrically defined and validated per DS-25PE20–139D–2/2022.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable; initiates all commands on high-to-low transition and terminates on low-to-high |
| SCK | Serial Clock | Input clock; latches SI on rising edge, clocks SO on falling edge - defines timing for all SPI transfers |
| SI | Serial Input | Command/address/data input path; ignored when CS is deasserted |
| SO | Serial Output | Data output path; tri-stated when CS is high - enables multi-device SPI bus sharing |
| WP | Write Protect | Hardware lock; prevents program/erase when asserted low - provides fail-safe protection independent of software state |
| RESET | Reset | Active-low hard reset; aborts ongoing operation and returns state machine to idle - critical for recovery after brown-out |
| VCC | Power Supply | 1.65V–3.6V input; powers all internal circuitry including charge pumps for erase/program |
| GND | Ground | Reference return path; must be low-impedance connection to system ground plane |
Key Features
| Feature | Design Value |
|---|---|
| RapidS™ interface | Enables 85 MHz continuous read - reduces boot time by >3× vs. standard SPI Flash at same density |
| Configurable page size | 256-byte default or 264-byte option - balances alignment efficiency with E²PROM emulation granularity |
| Dual-mode continuous read | Separate opcodes for high-speed (0Bh), low-power (01h), and legacy (E8h) - allows runtime optimization per system state |
| Integrated SRAM buffer | 256/264-byte scratchpad - eliminates need for external RAM in simple data buffering or firmware staging |
| Hardware + software write protection | WP pin + Sector Protection Register - provides layered security against accidental or malicious corruption |
Applications
| Industrial PLC Firmware Storage | Medical Device Data Logging |
|---|---|
Use Scenario: Storing and updating ladder logic firmware in compact programmable logic controllers with limited PCB real estate. IC Role / Device Role / Timing Role: Non-volatile program code storage with in-system reprogrammability via SPI; supports rapid field updates without removing the module. Use Value: 85 MHz RapidS™ read enables sub-100ms boot time; 300 nA deep power-down extends backup battery life during maintenance outages. | Use Scenario: Recording patient vital sign timestamps and sensor readings in portable ECG monitors operating on coin-cell batteries. IC Role / Device Role / Timing Role: High-endurance data buffer with E²PROM emulation - stores timestamped records using page-level read-modify-write. Use Value: 100,000 program/erase cycles per page ensures >5 years of daily logging; 20-year data retention guarantees audit compliance. |
| Smart Meter Firmware Vault | Automotive Telematics Bootloader |
Use Scenario: Securing utility meter firmware against unauthorized modification while supporting OTA updates over narrowband RF links. IC Role / Device Role / Timing Role: Protected code storage with hardware WP pin and 128-byte factory-unique ID - used for cryptographic key binding and version validation. Use Value: Dual protection (WP + Sector Protection Register) prevents tampering during update windows; JEDEC ID enables automated BOM verification. | Use Scenario: Hosting bootloader code in automotive infotainment head units requiring ASIL-B-aligned reliability and fast cold-start performance. IC Role / Device Role / Timing Role: Primary boot memory accessed directly by MCU on power-up; supports continuous read across page boundaries for zero-wait-state execution. Use Value: 6 ns clock-to-output (tV) minimizes instruction fetch latency; industrial temperature range (−40°C to +85°C) ensures operation under hood conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q20EW | 2-Mbit, 1.7V–2.0V supply only; no Ultra-Deep Power-Down (300 nA); no hardware WP pin | Lacks hardware write protection and ultra-low sleep current - unsuitable for battery-backed or safety-critical systems | Select AT25PE20-SSHN-B when hardware-level write lock and <1 µA sleep current are required. |
| Macronix MX25L2006E | 2-Mbit, 2.7V–3.6V supply; supports DTR mode but no RapidS™; 1 µA deep power-down (vs. 300 nA) | Higher minimum VCC excludes 1.8V-only designs; slower max clock (104 MHz DDR ≠ 85 MHz single-data-rate throughput) | Choose AT25PE20-SSHN-B for 1.65V operation, lower power-down current, and guaranteed 85 MHz single-ended read performance. |
Compared with W25Q20EW and MX25L2006E, AT25PE20-SSHN-B uniquely delivers 1.65V operation, 300 nA deep power-down, hardware WP, and RapidS™-optimized timing - making it the only option qualified for ultra-low-power, safety-aware, and mixed-voltage embedded systems.
Availability
AT25PE20-SSHN-B is available at Aetrix Electronics and suitable for industrial PLC firmware storage, medical device data logging, smart meter firmware vaults, automotive telematics bootloaders, and portable sensor node code hosting requiring stable component supply across extended product lifecycles.
Supply support for AT25PE20-SSHN-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Adesto Technologies (now part of Dialog Semiconductor, Renesas Electronics) specialized in low-power, high-reliability non-volatile memory and IoT interface solutions before acquisition in 2020.
The AT25PE20-SSHN-B belongs to the DataFlash-L® family - designed specifically for sequential-access, high-endurance, low-voltage embedded applications where pin count, power budget, and firmware update robustness are critical constraints.
FAQ
What is the maximum clock frequency supported by AT25PE20-SSHN-B in RapidS™ mode?
The AT25PE20-SSHN-B supports up to 85 MHz in RapidS™ mode (opcode 0Bh), enabling high-throughput continuous reads for fast boot and streaming applications. This is specified as fCAR1 in the datasheet and validated across the full industrial temperature range (−40°C to +85°C). The AT25PE20-SSHN-B achieves this without requiring external voltage boosters or level translators due to its 1.65V–3.6V native supply range.
Does AT25PE20-SSHN-B support true byte-level programming, or is it page-limited?
The AT25PE20-SSHN-B supports true byte-level programming within a page: the Buffer Write command allows loading 1–256/264 bytes into the SRAM buffer, and the Buffer to Main Memory Page Program command writes that subset to flash. While main memory erase is page/block/sector-level, the AT25PE20-SSHN-B's read-modify-write capability enables effective byte-alterable storage - essential for E²PROM emulation in parameter tables and calibration data.
How does the hardware Write Protect (WP) pin function on AT25PE20-SSHN-B?
The WP pin on AT25PE20-SSHN-B is an active-low hardware lock that independently disables all program and erase operations - even if software protection is disabled or compromised. When WP is asserted low, the AT25PE20-SSHN-B ignores incoming program/erase commands and remains in idle state. The pin is internally pulled high, so it may be left floating if unused, though external tie-to-VCC is recommended for noise immunity.
What package type and dimensions does AT25PE20-SSHN-B use?
AT25PE20-SSHN-B is packaged in an 8-lead SOIC (0.208" wide), with body dimensions of 5.33 mm × 5.33 mm × 1.78 mm and standard 1.27 mm lead pitch. The "SSHN-B" suffix explicitly denotes this SOIC variant (vs. UDFN or 0.150" SOIC). It is Pb/Halide-free and RoHS-compliant, meeting J-STD-020 moisture sensitivity level 3.
Can AT25PE20-SSHN-B be used for E²PROM emulation, and how is it implemented?
Yes, AT25PE20-SSHN-B supports robust E²PROM emulation using its SRAM buffer and single-command read-modify-write flow. Data is loaded into the buffer via Buffer Write, modified in-place, then written to flash via Buffer to Main Memory Page Program. This avoids wear on unrelated pages and leverages the AT25PE20-SSHN-B's 100,000-cycle endurance per page - enabling reliable byte/bit updates in configuration registers and calibration storage without external EEPROM.
AT25PE20-SSHN-B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- -
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR (SLC)
- Memory Size:
- 2Mbit
- Memory Organization:
- 256K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 85 MHz
- Write Cycle Time - Word, Page:
- 8µs, 3ms
- Access Time:
- 6 ns
- Voltage - Supply:
- 1.65V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25PE20-SSHN-B FAQ
1.How can I place an order for AT25PE20-SSHN-B through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25PE20-SSHN-B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25PE20-SSHN-B reliable?
The price and inventory of AT25PE20-SSHN-B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25PE20-SSHN-B is usually 5 days.
3.What payment methods are accepted for AT25PE20-SSHN-B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25PE20-SSHN-B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25PE20-SSHN-B?
AT25PE20-SSHN-B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25PE20-SSHN-B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25PE20-SSHN-B?
For technical support, including AT25PE20-SSHN-B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25PE20-SSHN-B requirements.
6.How does Aetrix verify that AT25PE20-SSHN-B is sourced from the original manufacturer or authorized distributors?
All AT25PE20-SSHN-B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25PE20-SSHN-B meets industry standards.
7.What is the process for return or replacement of AT25PE20-SSHN-B?
All AT25PE20-SSHN-B units undergo pre-shipment inspection (PSI). If there is an issue with AT25PE20-SSHN-B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25PE20-SSHN-B part is unused and in its original packaging.
Return procedure for AT25PE20-SSHN-B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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