My Inquiry
My Account
Renesas AT25QL128A-UUE-T
- Part No.:
- AT25QL128A-UUE-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 21-UFBGA, WLCSP
- Datasheet:
-
AT25QL128A-UUE-T.pdf
- Description:
- IC FLASH 128MBIT SPI 21WLCSP
- Quantity:
- Payment:
- Shipping:
Inventory:3,417
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25QL128A-UUE-T from Renesas Electronics is a 128-Mbit serial NOR Flash memory IC operating from a single 1.7–2.0 V supply, supporting SPI, Dual I/O, Quad I/O, and QPI interfaces with up to 133 MHz clock frequency and 6 ns clock-to-output timing. It delivers up to 65 Mbytes/s continuous read throughput and is used for code shadowing and firmware storage in embedded microcontrollers and IoT edge devices.
For engineers reviewing the AT25QL128A-UUE-T datasheet, AT25QL128A-UUE-T pinout, AT25QL128A-UUE-T application, or AT25QL128A-UUE-T equivalent, key selection criteria include quad I/O support, 4-kB/32-kB/64-kB flexible erase granularity, 2 µA deep power-down current, SFDP register compliance, and industrial temperature operation (–40 °C to +85 °C).
Technical Context
The AT25QL128A-UUE-T implements a unified command set across SPI, Dual I/O, Quad I/O, and QPI modes, with factory-default quad enable (QE) active. Its memory array comprises 65,536 pages of 256 bytes each, organized into physical blocks supporting independent 4-kB, 32-kB, and 64-kB erases - enabling efficient code partitioning and data logging without over-erasure.
It integrates hardware write protection via WP pin, dual status registers with configurable block protection (BP2–BP0), SRP1/SRP0-based status register lock, and a 4-kbit secured OTP register accessible only after entering secured mode (B1h). Erase/program suspend/resume capability enables concurrent background operations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 Mbit (16 MB), organized as 65,536 × 256-byte pages - supports full firmware images for mid-tier MCUs. |
| Interface Modes | SPI (Modes 0/3), Dual I/O, Quad I/O, and QPI - enables scalable bandwidth from 133 MHz single-line to 532 MHz effective quad-rate reads. |
| Max Read Throughput | 65 Mbytes/s continuous - sufficient for real-time boot code streaming or OTA update buffering. |
| Erase Granularity | 4-kB, 32-kB, and 64-kB blocks - allows precise firmware section updates without disturbing adjacent code or configuration data. |
| Page Program Time | 0.6 ms typical (256 bytes) - enables fast field firmware patching and runtime parameter storage. |
| Deep Power-Down Current | 2 µA typical - extends battery life in always-on sensor nodes and low-duty-cycle edge devices. |
| Data Retention | 20 years - meets long-lifecycle requirements for industrial controllers and medical equipment. |
| Operating Temp | –40 °C to +85 °C - qualified for under-hood automotive modules and factory-floor automation systems. |
Pinout & Package
AT25QL128A-UUE-T is supplied in an 8-pad DFN package (6 mm × 5 mm × 0.6 mm), RoHS-compliant and halide-free. Pin assignments are validated per datasheet Figure 1 and Table 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS# | Chip Select | Active-low enable for SPI/QPI command decoding; must be asserted before clock edge for valid instruction latching. |
| SO / IO1 | Serial Output / Quad I/O 1 | Output during standard/fast read; bidirectional in Quad I/O mode for address/data multiplexing. |
| WP# | Write Protect | Hardware lock for status register and memory blocks when driven low; overrides software write-enable state. |
| GND | Ground | Reference return path for all I/O and core logic; requires low-impedance PCB plane connection. |
| VCC | Power Supply | 1.7–2.0 V core and I/O supply; bypass capacitor (≥1 µF) required within 5 mm of pin. |
| HOLD# | Hold Control | Pauses ongoing read or program operation without deselecting device; retains internal address pointer. |
| SI / IO0 | Serial Input / Quad I/O 0 | Input for commands/addresses/data in SPI mode; bidirectional in Quad I/O for full-duplex transfers. |
| SCK | Serial Clock | Master-generated clock up to 133 MHz; timing critical for tV1 (6 ns) output hold specification. |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O & QPI Support | Enables 4x data bandwidth vs. standard SPI, reducing boot time and improving OTA update efficiency in resource-constrained hosts. |
| Flexible Erase Architecture | Independent 4-kB, 32-kB, and 64-kB erase blocks minimize wasted space during partial firmware updates and dynamic data logging. |
| Secured OTP Register | 4-kbit one-time programmable area stores cryptographic keys or calibration data with hardware-enforced write locking after B1h entry. |
| SFDP Register Compliance | Standardized JEDEC JESD216-compatible parameter table allows automatic host driver configuration without hard-coded timing values. |
| Erase/Program Suspend | Allows high-priority read operations to interrupt background erase or program, maintaining system responsiveness during firmware updates. |
| Industrial Temperature Range | Validated operation from –40 °C to +85 °C ensures reliability in uncontrolled environments like smart meters and motor drives. |
Applications
| Boot Code Storage | Firmware Over-the-Air (OTA) |
|---|---|
Use Scenario: Storing primary bootloader and application firmware for ARM Cortex-M or RISC-V microcontrollers. IC Role / Device Role / Timing Role: Non-volatile code storage with fast random-access read and deterministic page-program timing. Use Value: Enables zero-latency boot via XIP-capable host interfaces and supports secure firmware authentication using OTP-stored public keys. | Use Scenario: Receiving and validating encrypted firmware patches in connected industrial sensors and gateways. IC Role / Device Role / Timing Role: High-reliability update target with suspend/resume capability to avoid corruption during power loss. Use Value: 4-kB block erase granularity permits atomic patch application without disrupting active runtime code sections. |
| Configuration & Calibration Data | Edge AI Model Caching |
Use Scenario: Storing device-specific calibration coefficients, network credentials, and user preferences in medical wearables. IC Role / Device Role / Timing Role: Low-power, byte-addressable nonvolatile storage with hardware write protection against accidental overwrite. Use Value: WP# pin and BP bits allow permanent lockdown of critical parameters after factory programming. | Use Scenario: Caching quantized neural network weights for inference acceleration in battery-powered vision sensors. IC Role / Device Role / Timing Role: High-throughput sequential read buffer supporting burst-mode DMA transfers to AI accelerator memory. Use Value: 65 Mbytes/s Quad I/O read rate sustains >10 FPS inference on lightweight CNN models without DRAM bottleneck. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q128JVSIM | 3.3 V supply (vs. 1.7–2.0 V); identical 128-Mbit density, QPI, and SFDP support; 104 MHz max clock. | Requires level-shifting in 1.8 V systems; suitable for legacy 3.3 V designs with existing Winbond driver stack. | Select when board already uses 3.3 V I/O rails and Winbond ecosystem compatibility is prioritized. |
| Micron MT25QL128ABA8E12-0SIT | Same 1.7–2.0 V supply and 133 MHz QPI; includes additional security features (secure OTP, unique ID) and extended -40°C to +105°C option. | Better suited for automotive AEC-Q100-qualified designs requiring enhanced security or wider temperature margin. | Choose for safety-critical or extended-temperature deployments where Micron's qualification documentation is mandated. |
Compared with W25Q128JVSIM and MT25QL128ABA8E12-0SIT, the AT25QL128A-UUE-T offers optimal balance of ultra-low voltage operation, industrial temperature compliance, and proven integration in Renesas MCU reference designs - making it ideal for next-generation 1.8 V embedded systems requiring minimal power and robust firmware integrity.
Availability
AT25QL128A-UUE-T is available at Aetrix Electronics and suitable for boot code storage, firmware OTA updates, and configuration data retention requiring stable component supply across industrial, medical, and IoT production programs.
Supply support for AT25QL128A-UUE-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering trusted microcontrollers, analog, power, and memory solutions for automotive, industrial, infrastructure, and IoT markets.
The AT25QL128A-UUE-T belongs to Renesas' serial NOR Flash product line, engineered specifically for low-voltage, high-reliability firmware and data storage in resource-constrained embedded systems.
FAQ
What interface protocols does the AT25QL128A-UUE-T support?
The AT25QL128A-UUE-T supports standard SPI (Modes 0 and 3), Dual I/O, Quad I/O, and QPI protocols. Factory default enables Quad I/O mode, and QPI can be activated via the 38h command. All modes share a unified command set defined in datasheet Tables 8–11, ensuring consistent host driver implementation across interface choices.
Does the AT25QL128A-UUE-T include hardware write protection?
Yes, the AT25QL128A-UUE-T provides hardware write protection via the dedicated WP# pin, which locks status register bits and memory blocks when pulled low. This operates independently of software write-enable states and complements configurable block protection (BP2–BP0) and status register protect (SRP1/SRP0) bits for multi-layer firmware security.
What is the purpose of the secured OTP register in the AT25QL128A-UUE-T?
The AT25QL128A-UUE-T includes a 4-kbit secured One-Time Programmable (OTP) register used to store immutable data such as cryptographic keys, device identifiers, or calibration constants. Access requires issuing the Enter Secured OTP (B1h) command; once programmed, bits cannot be altered, ensuring tamper-resistant storage critical for secure boot and device authentication workflows.
How does the AT25QL128A-UUE-T handle power-down to minimize current draw?
The AT25QL128A-UUE-T supports Deep Power-Down mode (B9h command), reducing typical standby current to 2 µA. In this state, all internal circuitry except wake-up logic is disabled. The device exits via Release Deep Power-Down (ABh), with guaranteed wake-up time ≤100 µs - enabling aggressive power gating in battery-operated edge nodes without sacrificing responsiveness.
Is the AT25QL128A-UUE-T compatible with JEDEC-standard Serial Flash Discovery Parameters (SFDP)?
Yes, the AT25QL128A-UUE-T implements JEDEC JESD216-compliant SFDP register (accessible via 5Ah command), providing standardized tables of timing parameters, erase block structures, and feature flags. This enables automatic host driver initialization without hardcoded timing values, simplifying portability across different microcontroller platforms and reducing firmware development effort for the AT25QL128A-UUE-T.
AT25QL128A-UUE-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 21-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 150µs, 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 2V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 21-WLCSP (3.02x3.29)
AT25QL128A-UUE-T FAQ
1.How can I place an order for AT25QL128A-UUE-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25QL128A-UUE-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25QL128A-UUE-T reliable?
The price and inventory of AT25QL128A-UUE-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25QL128A-UUE-T is usually 5 days.
3.What payment methods are accepted for AT25QL128A-UUE-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25QL128A-UUE-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25QL128A-UUE-T?
AT25QL128A-UUE-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25QL128A-UUE-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25QL128A-UUE-T?
For technical support, including AT25QL128A-UUE-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25QL128A-UUE-T requirements.
6.How does Aetrix verify that AT25QL128A-UUE-T is sourced from the original manufacturer or authorized distributors?
All AT25QL128A-UUE-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25QL128A-UUE-T meets industry standards.
7.What is the process for return or replacement of AT25QL128A-UUE-T?
All AT25QL128A-UUE-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25QL128A-UUE-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25QL128A-UUE-T part is unused and in its original packaging.
Return procedure for AT25QL128A-UUE-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25QL128A-UUE-T Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
