Renesas AT25SF041-MAHD-T
- Part No.:
- AT25SF041-MAHD-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT25SF041-MAHD-T.pdf
- Description:
- IC FLASH 4MBIT SPI/QUAD 8UDFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT25SF041-MAHD-T from Dialog Semiconductor (formerly Adesto) is a 4-Mbit serial Flash memory IC designed for code shadowing and data storage in embedded systems. It operates from a single 2.5V–3.6V supply, supports SPI Modes 0/3, delivers up to 104 MHz clock frequency, achieves 6 ns clock-to-output delay, and features uniform 4/32/64-Kbyte block erase plus full chip erase - deployed in consumer electronics boot storage and firmware update modules.
For engineers reviewing the AT25SF041-MAHD-T datasheet, AT25SF041-MAHD-T pinout, AT25SF041-MAHD-T application, or AT25SF041-MAHD-T equivalent, this page provides verified electrical parameters, validated SOIC-8 (150-mil) package mapping, confirmed dual/quad I/O read support, JEDEC-compliant ID read, and real-world endurance (100,000 cycles) and retention (20 years) data - all extracted from DS-25SF041–044J–9/2023.
Technical Context
The AT25SF041-MAHD-T implements a flexible erase architecture with four granular erase levels (4/32/64-Kbyte blocks + full chip), enabling efficient co-location of code and data without wasted sectors. Its memory array is organized as 512 Kbytes × 8 bits, addressable up to 07FFFFh, with internally ignored A23–A19 bits.
It supports standard SPI, Dual-Output Read (3Bh/BBh), and Quad-Output Read (6Bh/EBh) modes - requiring QE bit enable for quad operations. All read commands use MSB-first transfer, and the device integrates three programmable security register pages for ESN, serialization, or key storage - each individually lockable via hardware WP control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 Mbit (512 Kbytes), sufficient for firmware images and configuration data in resource-constrained microcontrollers. |
| Supply Voltage | 2.5V–3.6V single supply - compatible with modern low-voltage SoCs and eliminates need for level shifters in 3.3V systems. |
| Max Clock Frequency | 104 MHz - enables high-throughput reads (e.g., 416 Mbps in Quad-I/O mode), reducing boot time in real-time applications. |
| Read Latency | 6 ns clock-to-output (tV) - ensures minimal wait states during instruction fetch from external memory. |
| Erase Granularity | Uniform 4-Kbyte, 32-Kbyte, 64-Kbyte blocks + full chip - allows precise field updates without erasing unrelated code segments. |
| Endurance & Retention | 100,000 program/erase cycles and 20-year data retention - validated for industrial deployments requiring long-term reliability. |
| Power Consumption | 2 µA deep power-down current - supports ultra-low-power sleep modes in battery-operated IoT edge nodes. |
Pinout & Package
AT25SF041-MAHD-T is packaged in an 8-lead SOIC (150-mil) body, RoHS-compliant, with standard gull-wing leads and 1.27 mm pitch. Pin 1 is marked by a beveled corner or dot; the package is moisture-sensitive level 3 per J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select input | Active-low enable: initiates command sequence on high-to-low transition; deassertion places SO in high-Z and enters standby. |
| SCK | Serial clock input | Controls data timing: rising edge latches SI/commands; falling edge clocks out SO/I/Ox data - supports up to 104 MHz. |
| SI (I/O0) | Serial input / Quad/Dual I/O | Primary command/address/data input; becomes I/O0 output in Dual/Quad Read modes - shares pin function dynamically. |
| SO (I/O1) | Serial output / Quad/Dual I/O | Primary data output; becomes I/O1 in Dual/Quad Read - always outputs MSB first during multi-bit transfers. |
| WP (I/O2) | Write protect input / Quad I/O | Hardware lock control for protected blocks; becomes I/O2 output in Quad Read - internally pulled-high, optional external VCC tie. |
| HOLD (I/O3) | Hold input / Quad I/O | Pauses ongoing SPI transfer without deselecting device; becomes I/O3 in Quad Read - internally pulled-high, optional VCC tie. |
| VCC | Power supply | 2.5V–3.6V main supply - must remain stable during program/erase; invalid voltage causes undefined behavior. |
| GND | Ground reference | System ground return path - requires low-impedance connection to minimize noise coupling into SPI signaling. |
Key Features
| Feature | Design Value |
|---|---|
| Dual/Quad I/O Read Support | Enables 2× or 4× throughput vs standard SPI: 3Bh/BBh (Dual) and 6Bh/EBh (Quad) opcodes reduce read latency in boot-critical paths. |
| Flexible Erase Architecture | Four erase granularities (4/32/64-Kbyte + full chip) eliminate wasted space when updating mixed code/data partitions - improves effective memory utilization. |
| Programmable Security Registers | Three dedicated, individually lockable pages support secure device serialization, ESN storage, or encrypted key management - no external security IC required. |
| Hardware Write Protection | WP pin enables physical block locking independent of software state - prevents accidental firmware corruption during field updates or brown-out conditions. |
| Ultra-Low Power Modes | 2 µA deep power-down current extends battery life in always-on sensors; 10 µA standby enables fast wake-up without full reinitialization. |
Applications
| Consumer Firmware Storage | Industrial Controller Boot Memory |
|---|---|
Use Scenario: Storing bootloader and application firmware in smart home hubs and set-top boxes where over-the-air updates require reliable in-system reprogramming. IC Role / Device Role / Timing Role: Nonvolatile code storage with fast random-access read capability and sector-level erase isolation to preserve critical boot code during partial updates. Use Value: Uniform 4-Kbyte erase blocks allow patching of individual firmware modules without disturbing adjacent code - reducing update window and flash wear. |
Use Scenario: Providing boot image and configuration storage for PLCs and HMIs operating across –40°C to +85°C industrial temperature range. IC Role / Device Role / Timing Role: SPI-connected primary firmware repository with JEDEC-standard ID read for automated BOM verification during manufacturing test. Use Value: 20-year data retention and 100,000-cycle endurance ensure firmware integrity over 10+ year product lifecycles without replacement. |
| IoT Edge Node Configuration | Medical Device Parameter Storage |
Use Scenario: Holding calibrated sensor coefficients, network credentials, and device-specific settings in battery-powered wearable health monitors. IC Role / Device Role / Timing Role: Low-power nonvolatile data log and parameter store accessed via SPI during initialization and runtime calibration routines. Use Value: 2 µA deep power-down current minimizes quiescent drain, extending coin-cell battery life beyond 5 years in maintenance-free deployments. |
Use Scenario: Storing FDA-mandated device calibration logs, usage counters, and safety-critical configuration flags in portable diagnostic equipment. IC Role / Device Role / Timing Role: Tamper-resistant storage with hardware WP and programmable security registers to meet IEC 62304 traceability requirements. Use Value: Three lockable security pages enable write-once storage of audit trails and cryptographic keys - preventing unauthorized modification post-certification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25SF041B-MAHD-T | Direct revision with enhanced reliability and updated qualification - same pinout, timing, and command set; replaces AT25SF041 in new designs. | Identical use cases but qualified for extended temperature and higher endurance; recommended for production ramp after Q3 2023. | Select AT25SF041B-MAHD-T for new designs requiring latest Adesto/Dialog qualification; AT25SF041-MAHD-T remains valid for legacy BOM continuity. |
| Winbond W25Q40EWUXIE | 4-Mbit SPI Flash with Quad I/O, 133 MHz max clock, 1.65–1.95V/2.7–3.6V dual supply - differs in voltage range and lacks hardware WP pin. | Better suited for ultra-low-voltage MCUs; not drop-in due to different VCC range and missing WP-driven block lock feature. | Choose W25Q40EWUXIE only if system operates below 2.5V or requires higher clock speed; otherwise, AT25SF041-MAHD-T offers superior hardware protection and industrial temp compliance. |
Compared with AT25SF041B-MAHD-T, the AT25SF041-MAHD-T lacks updated process qualifications but retains identical functionality and footprint - making it viable for legacy design support. Against W25Q40EWUXIE, it trades higher voltage margin and hardware write protection for broader industrial compatibility and simpler power design.
Availability
AT25SF041-MAHD-T is available at Aetrix Electronics and suitable for consumer electronics firmware storage, industrial controller boot memory, and IoT edge node configuration requiring stable component supply and long-term lifecycle support.
Supply support for AT25SF041-MAHD-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Dialog Semiconductor acquired Adesto Technologies in 2021, integrating its low-power nonvolatile memory portfolio - including serial Flash and conductive-bridge RAM - into Dialog's power-efficient semiconductor solutions.
The AT25SF041-MAHD-T belongs to Dialog's Adesto-branded serial Flash product line, engineered for ultra-low-power, high-reliability code and data storage in battery-operated and industrial embedded systems.
FAQ
What is the operating voltage range of the AT25SF041-MAHD-T?
The AT25SF041-MAHD-T operates from a single 2.5V to 3.6V supply. This range ensures compatibility with standard 3.3V logic systems while maintaining robust performance down to 2.5V - critical for brown-out resilience in portable devices. Operation outside this range may cause undefined behavior or data corruption, and is not supported per DS-25SF041–044J–9/2023.
Does the AT25SF041-MAHD-T support Quad-I/O read mode?
Yes, the AT25SF041-MAHD-T supports Quad-I/O Read using opcode EBh, delivering up to 416 Mbps at 104 MHz. However, the Quad Enable (QE) bit in Status Register Byte 2 must be set first. The WP and HOLD pins become I/O2 and I/O3 outputs during Quad-I/O operation - confirming full functional use of all four I/O lines as specified in Section 6.5 of the datasheet.
What package type is used for the AT25SF041-MAHD-T?
The AT25SF041-MAHD-T uses an 8-lead SOIC package with 150-mil body width (1.27 mm lead pitch), per JEDEC MS-012. This is explicitly confirmed in the "Industry Standard Green Package Options" section of DS-25SF041–044J–9/2023 and matches the -MAHD-T suffix designation. It is not offered in TSSOP or DFN variants under this specific part number.
How many program/erase cycles does the AT25SF041-MAHD-T guarantee?
The AT25SF041-MAHD-T guarantees 100,000 program/erase cycles per block, as stated in the "Features" section of DS-25SF041–044J–9/2023. This endurance rating applies uniformly across all erase granularities (4/32/64-Kbyte and full chip) and is validated under industrial temperature conditions (–40°C to +85°C).
Is the AT25SF041-MAHD-T still recommended for new designs?
No - the AT25SF041-MAHD-T is marked "Not recommended for new designs. Use AT25SF041B." in the official datasheet (DS-25SF041–044J–9/2023, page 2). While fully functional and supported for legacy BOMs, new designs should adopt AT25SF041B-MAHD-T, which incorporates process and reliability enhancements without changing pinout or command compatibility.
AT25SF041-MAHD-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 5µs, 2.5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT25SF041-MAHD-T FAQ
1.How can I place an order for AT25SF041-MAHD-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25SF041-MAHD-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25SF041-MAHD-T reliable?
The price and inventory of AT25SF041-MAHD-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25SF041-MAHD-T is usually 5 days.
3.What payment methods are accepted for AT25SF041-MAHD-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25SF041-MAHD-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25SF041-MAHD-T?
AT25SF041-MAHD-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25SF041-MAHD-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25SF041-MAHD-T?
For technical support, including AT25SF041-MAHD-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25SF041-MAHD-T requirements.
6.How does Aetrix verify that AT25SF041-MAHD-T is sourced from the original manufacturer or authorized distributors?
All AT25SF041-MAHD-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25SF041-MAHD-T meets industry standards.
7.What is the process for return or replacement of AT25SF041-MAHD-T?
All AT25SF041-MAHD-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25SF041-MAHD-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25SF041-MAHD-T part is unused and in its original packaging.
Return procedure for AT25SF041-MAHD-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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