Renesas AT25SF041-SHDHR-T
- Part No.:
- AT25SF041-SHDHR-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
AT25SF041-SHDHR-T.pdf
- Description:
- IC FLASH 4MBIT SPI/QUAD 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:192
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Product details
Overview
AT25SF041-SHDHR-T from Dialog Semiconductor (formerly Adesto) is a 4-Mbit serial flash memory IC designed for code shadowing and data storage in embedded systems. It operates from a single 2.5V–3.6V supply, supports SPI Modes 0/3, delivers up to 104 MHz clock frequency, achieves 6 ns clock-to-output delay, and features uniform 4/32/64-Kbyte block erase plus full chip erase - deployed in consumer electronics boot firmware and IoT sensor node configuration storage.
For engineers reviewing the AT25SF041-SHDHR-T datasheet, AT25SF041-SHDHR-T pinout, AT25SF041-SHDHR-T application, or AT25SF041-SHDHR-T equivalent, key selection criteria include dual/quad I/O read throughput, hardware write protection via WP pin, security register programmability, industrial temperature support (−40°C to +85°C), and RoHS-compliant 8-lead SOIC (208-mil) packaging.
Technical Context
The AT25SF041-SHDHR-T implements a flexible SPI-based serial flash architecture with four erase granularities (4/32/64-Kbyte blocks + full chip), enabling efficient co-location of code modules and data segments without memory waste. Its dual- and quad-I/O read modes use SI/SO/WP/HOLD as bidirectional I/O pins under specific opcodes (3Bh/BBh/6Bh/EBh), requiring QE bit enablement in Status Register for quad operation.
It integrates three programmable, individually lockable security register pages for ESN storage or key management, and supports byte/page programming (1–256 bytes) with typical 0.7 ms page program time. Deep power-down current is 2 µA (typ), supporting battery-backed applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 Mbit (512 Kbytes) - sufficient for firmware images and persistent configuration in compact MCU-based devices. |
| Supply Voltage | 2.5V–3.6V - compatible with modern low-voltage microcontrollers and eliminates need for level-shifting in 3.3V systems. |
| Max Clock Frequency | 104 MHz - enables high-speed instruction fetch and reduces boot latency in real-time applications. |
| Read Latency | 6 ns tV (clock-to-output) - ensures minimal wait states during sequential code execution from flash. |
| Erase Granularity | Uniform 4/32/64-Kbyte blocks + full chip - allows precise field-upgrade of firmware sections without erasing entire image. |
| Endurance & Retention | 100,000 program/erase cycles / 20 years data retention - meets long-life requirements for industrial and automotive ECUs. |
| Operating Temperature | −40°C to +85°C - certified for full industrial range, suitable for uncontrolled ambient deployments. |
| Power Consumption | 2 µA deep power-down (typ), 10 µA standby (typ), 4 mA active read (typ) - optimized for energy-constrained edge nodes. |
Pinout & Package
AT25SF041-SHDHR-T is packaged in an 8-lead SOIC (208-mil) body, measuring 5.3 mm × 5.3 mm × 1.95 mm, with gull-wing leads and Pb/Halide-free/RoHS-compliant finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select input | Active-low enable signal; rising edge terminates operations and places SO in high-impedance state. |
| SCK | Serial clock input | Controls data timing; rising edge latches command/address/data on SI; falling edge clocks data out on SO/I/Ox. |
| SI (I/O0) | Serial input / Quad/Dual I/O | Primary command/address/data input; becomes output (I/O0) during Dual/Quad Read for parallel bit streaming. |
| SO (I/O1) | Serial output / Quad/Dual I/O | Primary data output; becomes output (I/O1) during Dual/Quad Read; MSB always appears on SO first. |
| WP (I/O2) | Write protect input / Quad I/O | Hardware lock control for protected blocks; becomes I/O2 output during Quad Read; internally pulled high. |
| HOLD (I/O3) | Communication hold input / Quad I/O | Pauses ongoing transfers without deselecting device; becomes I/O3 output during Quad Read; internally pulled high. |
| VCC | Power supply | 2.5V–3.6V main supply; powers core logic, I/O buffers, and charge pump for programming/erasing. |
| GND | Ground reference | System ground return path; must be low-impedance and decoupled near VCC pin for noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Dual/Quad I/O Read Support | Enables 2× or 4× read bandwidth vs standard SPI - reduces firmware load time by up to 75% at same clock rate. |
| Flexible Erase Architecture | Four uniform erase block sizes eliminate wasted space when updating mixed code/data partitions - improves effective memory utilization. |
| Three Security Register Pages | Individually programmable and lockable pages store ESNs, cryptographic keys, or calibration data - prevents unauthorized access post-deployment. |
| Hardware Write Protection | WP pin enables physical locking of memory sectors - prevents accidental overwrite during field updates or brown-out conditions. |
| Low-Power Deep Power-Down | 2 µA typical current draw extends battery life in always-on sensors and wearables without sacrificing fast wake-up (<10 µs). |
| JEDEC ID & Security Commands | Standard manufacturer/device ID (9Fh) and dedicated security opcodes (42h/44h/48h) simplify BOM validation and secure provisioning workflows. |
Applications
| Consumer Electronics Boot Storage | Industrial PLC Firmware |
|---|---|
|
Use Scenario: Storing bootloader and application firmware in smart home hubs and set-top boxes. IC Role / Device Role / Timing Role: Non-volatile code storage with fast random-access read for shadowing into RAM at power-up. Use Value: 104 MHz Quad-I/O read and 6 ns tV reduce boot time by >40% vs legacy 50 MHz SPI flash, improving user experience. |
Use Scenario: Holding firmware and configuration data in programmable logic controllers operating in factory environments. IC Role / Device Role / Timing Role: Field-upgradable code and parameter storage with hardware write protection against EMI-induced corruption. Use Value: Uniform 4-Kbyte block erase allows patching individual function modules without reprogramming entire firmware image. |
| IoT Sensor Node Configuration | Medical Device Calibration Data |
|
Use Scenario: Persisting network credentials, sensor calibration offsets, and OTA update staging in battery-powered environmental monitors. IC Role / Device Role / Timing Role: Low-power non-volatile data storage with deep power-down mode synchronized to sensor sampling intervals. Use Value: 2 µA deep power-down current extends 2-AA battery life beyond 5 years while retaining critical settings. |
Use Scenario: Securing device-specific calibration coefficients and regulatory compliance metadata in portable diagnostic tools. IC Role / Device Role / Timing Role: Tamper-resistant storage using programmable security register pages with individual lock bits. Use Value: Three lockable security pages prevent unauthorized modification of FDA/CE-critical calibration parameters during service. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25SF041B-SHDHR-T | Successor variant with enhanced reliability, updated process node, and extended lifecycle support; identical pinout and command set. | Recommended for new designs per Dialog's obsolescence notice; offers longer production availability and improved ESD robustness. | Select AT25SF041B-SHDHR-T for new projects requiring long-term supply continuity and latest qualification standards. |
| Winbond W25Q40EWUXIE | 4-Mbit SPI flash with Quad I/O, 133 MHz max clock, but lacks security register pages and uses different status register layout. | Suitable for cost-sensitive consumer applications where security features are not required and firmware update protocols are vendor-agnostic. | Choose W25Q40EWUXIE only if security register functionality is unnecessary and existing driver software supports Winbond-specific status bits. |
Compared with AT25SF041-SHDHR-T, the AT25SF041B-SHDHR-T provides guaranteed long-term availability and process improvements without design changes, while the W25Q40EWUXIE trades security and compatibility for higher clock speed and broader distributor stock - making it viable only where Adesto-specific features are unused.
Availability
AT25SF041-SHDHR-T is available at Aetrix Electronics and suitable for consumer electronics boot storage, industrial PLC firmware, IoT sensor node configuration, and medical device calibration data applications requiring stable component supply across multi-year production cycles.
Supply support for AT25SF041-SHDHR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Dialog Semiconductor acquired Adesto Technologies in 2021 and now owns and supports the AT25SF series of serial flash memory products.
The AT25SF product line was engineered for high-reliability, low-power embedded code and data storage - targeting resource-constrained IoT endpoints, industrial controllers, and medical devices needing secure, long-life non-volatile memory.
FAQ
What is the maximum operating frequency supported by the AT25SF041-SHDHR-T?
The AT25SF041-SHDHR-T supports a maximum clock frequency of 104 MHz for Quad-I/O and Dual-I/O read operations, and up to 85 MHz for standard Read Array (0Bh) and Dual-Output Read (3Bh). This enables high-throughput firmware loading and real-time data access in performance-critical embedded systems. The 104 MHz rating applies specifically when using Quad-I/O Read (6Bh/EBh) commands with QE bit enabled.
Does the AT25SF041-SHDHR-T support hardware write protection?
Yes, the AT25SF041-SHDHR-T supports hardware write protection via its WP pin. When asserted low, the WP pin enables hardware locking of protected memory blocks, preventing accidental program or erase operations. The device also supports software-controlled protection through status register bits, and the WP pin is internally pulled high - allowing it to float if unused, though external connection to VCC is recommended.
How many security register pages does the AT25SF041-SHDHR-T provide?
The AT25SF041-SHDHR-T provides three dedicated, programmable security register pages. Each page can be individually locked using hardware or software methods, supporting use cases such as unique device serialization, system-level Electronic Serial Number (ESN) storage, and secure key management. These pages are separate from main memory and accessed via dedicated opcodes (42h, 44h, 48h).
What package type is used for the AT25SF041-SHDHR-T?
The AT25SF041-SHDHR-T is supplied in an 8-lead SOIC package with 208-mil body width (5.3 mm × 5.3 mm × 1.95 mm), featuring gull-wing leads and RoHS-compliant, Pb/halide-free finish. This industry-standard package ensures drop-in compatibility with existing PCB footprints designed for 8-pin serial flash devices and supports automated SMT assembly.
Is the AT25SF041-SHDHR-T still recommended for new designs?
No - Dialog Semiconductor explicitly marks the AT25SF041-SHDHR-T as "Not recommended for new designs" and recommends migration to the AT25SF041B-SHDHR-T. While AT25SF041-SHDHR-T remains available for legacy support and existing production, the B-version offers extended lifecycle assurance, improved manufacturing process, and continued technical documentation and qualification support.
AT25SF041-SHDHR-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 5µs, 2.5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25SF041-SHDHR-T FAQ
1.How can I place an order for AT25SF041-SHDHR-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25SF041-SHDHR-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25SF041-SHDHR-T reliable?
The price and inventory of AT25SF041-SHDHR-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25SF041-SHDHR-T is usually 5 days.
3.What payment methods are accepted for AT25SF041-SHDHR-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25SF041-SHDHR-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25SF041-SHDHR-T?
AT25SF041-SHDHR-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25SF041-SHDHR-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25SF041-SHDHR-T?
For technical support, including AT25SF041-SHDHR-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25SF041-SHDHR-T requirements.
6.How does Aetrix verify that AT25SF041-SHDHR-T is sourced from the original manufacturer or authorized distributors?
All AT25SF041-SHDHR-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25SF041-SHDHR-T meets industry standards.
7.What is the process for return or replacement of AT25SF041-SHDHR-T?
All AT25SF041-SHDHR-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25SF041-SHDHR-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25SF041-SHDHR-T part is unused and in its original packaging.
Return procedure for AT25SF041-SHDHR-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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