Renesas AT25SF161B-SHB-B
- Part No.:
- AT25SF161B-SHB-B
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
AT25SF161B-SHB-B.pdf
- Description:
- IC FLASH 16MBIT SPI/QUAD 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT25SF161B-SHB-B from Renesas Electronics is a 16-Mbit SPI serial flash memory IC supporting dual I/O and quad I/O operations, 108 MHz max clock frequency, 2.5–3.6 V supply, and execute-in-place (XiP) capability for embedded boot and code storage. It features 4 kB/32 kB/64 kB block erase, 256-byte page programming, and OTP security registers.
For engineers reviewing the AT25SF161B-SHB-B datasheet, AT25SF161B-SHB-B pinout, AT25SF161B-SHB-B application, or AT25SF161B-SHB-B equivalent, key selection criteria include quad-SPI timing compliance (1-4-4, 0-4-4), deep power-down current (≤1.5 µA), SFDP register support, and JEDEC-standard manufacturer/device ID readback.
Technical Context
The AT25SF161B-SHB-B implements a flexible SPI interface with hardware-selectable modes (0 and 3), dual-output (1-1-2), dual-I/O (1-2-2), quad-output (1-1-4), and quad-I/O (1-4-4, 0-4-4) read protocols. Its internal architecture includes SRAM data buffers, Y/X decoders, and control logic enabling continuous read with wrap and program/erase suspend-resume functionality.
Memory protection is implemented via non-volatile status register bits (SRP0/SRP1), user-definable protected regions at array start/end, and WP pin assertion. Security is enhanced by three 256-byte OTP registers accessible via dedicated commands (42h/44h/48h/4Bh) and SFDP parameter table for host auto-configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 16 Mbit (2 MB) - supports firmware images up to 2 MiB in size without external expansion. |
| Max Clock Frequency | 108 MHz - enables fast sequential reads (e.g., XiP instruction fetch) with ≤9.3 ns cycle time. |
| Erase Time (4 kB block) | 50 ms typical - allows rapid field updates of small configuration or patch sectors. |
| Page Program Time | 0.4 ms typical for 1–256 bytes - supports low-latency runtime parameter writes. |
| Deep Power-Down Current | 1.5 µA maximum - extends battery life in always-on IoT edge nodes during idle periods. |
| Data Retention | 20 years - ensures long-term reliability for industrial control firmware storage. |
| Endurance | 100,000 program/erase cycles - suitable for logging or configuration storage with moderate write frequency. |
Pinout & Package
AT25SF161B-SHB-B is packaged in an 8-lead SOIC (0.208" wide, JEDEC MS-012), with pins arranged as follows:
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: CS | Chip Select | Active-low enable; must transition high-to-low to initiate command sequence and low-to-high to terminate. |
| 2: SO (I/O1) | Serial Output / Quad I/O Line 1 | Outputs data on falling SCK edge; functions as I/O1 in dual/quad I/O modes. |
| 3: WP (I/O2) | Write Protect / Quad I/O Line 2 | Configurable: protects status registers when QE=0 & SRP=01; serves as I/O2 when QE=1. |
| 4: GND | Ground Reference | System ground return path for all digital and power circuits; required for stable SPI signaling. |
| 5: VCC | Power Supply | 2.5–3.6 V input; powers core logic, I/O buffers, and flash array; requires local 100 nF decoupling. |
| 6: HOLD (I/O3) | Hold Input / Quad I/O Line 3 | Pauses ongoing SPI transfer without resetting state; functions as I/O3 in quad I/O mode when QE=1. |
| 7: SCK | Serial Clock | Master-generated clock; rising edge latches SI/I/O0, falling edge clocks SO/I/O1. |
| 8: SI (I/O0) | Serial Input / Quad I/O Line 0 | Accepts commands, addresses, and data on rising SCK edge; becomes I/O0 in dual/quad modes. |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O & XiP Support | Enables 0-4-4 continuous read mode for zero-overhead instruction execution directly from flash. |
| Erase/Program Suspend-Resume | Allows background erase or program to be paused for urgent read access, improving real-time system responsiveness. |
| Three 256-byte OTP Registers | Provides immutable storage for keys, calibration data, or device-unique identifiers with permanent write-lock capability. |
| Serial Flash Discoverable Parameters (SFDP) | Host can auto-detect timing, density, and command set via standardized 5Ah read, eliminating hard-coded initialization. |
| User-Definable Memory Protection | Allows software-defined lock/unlock of top or bottom memory regions (e.g., bootloader section) using SRP bits. |
Applications
| Industrial PLC Firmware Storage | Automotive Infotainment Boot Memory |
|---|---|
|
Use Scenario: Storing firmware images and configuration data in programmable logic controllers operating continuously in harsh environments. IC Role / Device Role / Timing Role: Non-volatile boot memory providing XiP-capable code execution and secure update partitioning. Use Value: 20-year data retention and 100,000-cycle endurance ensure reliable operation over 10+ year product lifecycles without refresh. |
Use Scenario: Hosting boot code and UI assets for head-unit systems requiring fast startup and secure OTA updates. IC Role / Device Role / Timing Role: Primary SPI flash for U-Boot and Linux kernel image storage with quad-I/O acceleration. Use Value: 108 MHz quad-I/O read speed reduces boot time by >40% versus standard SPI, meeting automotive cold-start requirements. |
| IoT Edge Node Configuration Storage | Medical Device Calibration Data Vault |
|
Use Scenario: Persisting network credentials, sensor calibration offsets, and device-specific settings in battery-powered wireless sensors. IC Role / Device Role / Timing Role: Low-power configuration store with deep power-down mode and byte-level write capability. Use Value: 1.5 µA deep power-down current extends coin-cell battery life to >5 years in sleep-dominated operation. |
Use Scenario: Securing factory-calibrated sensor coefficients and regulatory compliance metadata in portable diagnostic equipment. IC Role / Device Role / Timing Role: Tamper-resistant storage using OTP registers and hardware write-protection. Use Value: Three independent 256-byte OTP banks allow separation of calibration, serial number, and audit log data with irreversible locking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q16JVSNIQ | 16 Mbit, 133 MHz max, 2.7–3.6 V, same SOIC-8 package; lacks OTP registers and SFDP v1.6 support. | Supports faster quad reads but offers no hardware-based secure storage; requires external key management. | Select when maximum read throughput is critical and OTP security is handled in software or external crypto IC. |
| Micron MT25QL128ABA8ESF-0SIT | 128 Mbit (8× larger), 133 MHz, 2.7–3.6 V, SOIC-8; includes SFDP v1.6 and uniform 4 kB erase, but higher standby current (25 µA). | Suitable for larger firmware images; not drop-in compatible due to density mismatch and different status register layout. | Choose for future-proofing with scalable density and industry-standard QSPI compliance, accepting higher quiescent power. |
Compared with AT25SF161B-SHB-B, W25Q16JVSNIQ trades OTP security for higher speed, while MT25QL128ABA8ESF-0SIT provides greater capacity and broader QSPI standardization at the cost of increased standby power and non-interchangeable command mapping.
Availability
AT25SF161B-SHB-B is available at Aetrix Electronics and suitable for industrial PLC firmware storage, automotive infotainment boot memory, and IoT edge node configuration storage requiring stable component supply across multi-year production cycles.
Supply support for AT25SF161B-SHB-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog, power, and memory solutions for automotive, industrial, and IoT markets.
The AT25SF161B belongs to Renesas' AT25SF family of SPI flash devices engineered for high-reliability embedded boot and code storage, emphasizing XiP performance, low-power operation, and hardware-assisted security.
FAQ
What voltage range does the AT25SF161B-SHB-B support?
The AT25SF161B-SHB-B operates across two supply ranges: 2.7 V to 3.6 V and 2.5 V to 3.6 V. This dual-voltage capability allows direct integration into both legacy 3.3 V systems and newer low-power 2.5 V designs without level-shifting circuitry. The AT25SF161B-SHB-B maintains full specification compliance-including 108 MHz operation and 1.5 µA deep power-down-across the entire 2.5–3.6 V window.
Does the AT25SF161B-SHB-B support execute-in-place (XiP) operation?
Yes, the AT25SF161B-SHB-B explicitly supports XiP through quad-I/O read modes (1-4-4 and 0-4-4), continuous read with wrap, and high-speed 108 MHz clocking. These features eliminate opcode overhead and maximize instruction fetch bandwidth, enabling microcontrollers to execute code directly from flash without copying to RAM. The AT25SF161B-SHB-B datasheet confirms XiP suitability in its Product Overview section.
How many one-time programmable (OTP) registers does the AT25SF161B-SHB-B include?
The AT25SF161B-SHB-B integrates three independent 256-byte OTP security registers, accessible via dedicated commands (42h program, 44h erase, 48h read, 4Bh unique ID). Each register can be permanently locked after programming, making them ideal for storing cryptographic keys, calibration constants, or device-unique identifiers. This OTP capability is a distinguishing feature of the AT25SF161B-SHB-B versus generic SPI flash alternatives.
What package type is used for the AT25SF161B-SHB-B?
The AT25SF161B-SHB-B uses an 8-lead SOIC package with 0.208" body width (EIAJ standard), designated in Renesas' ordering information as "SHB-B". This package is pin-compatible with industry-standard 8-pin SOIC footprints and supports reflow soldering per J-STD-020. The "B" suffix indicates RoHS-compliant, halogen-free construction.
Does the AT25SF161B-SHB-B support Serial Flash Discoverable Parameters (SFDP)?
Yes, the AT25SF161B-SHB-B implements JEDEC-standard SFDP v1.6 via the 5Ah command, allowing hosts to dynamically discover supported commands, timing parameters, density, and erase granularity without hardcoded assumptions. This enables robust, vendor-agnostic flash initialization in bootloader and FPGA configuration firmware. The AT25SF161B-SHB-B's SFDP table includes entries for all supported read, program, and erase operations.
AT25SF161B-SHB-B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 16Mbit
- Memory Organization:
- 2M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 108 MHz
- Write Cycle Time - Word, Page:
- 50µs, 2.4ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT25SF161B-SHB-B FAQ
1.How can I place an order for AT25SF161B-SHB-B through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25SF161B-SHB-B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25SF161B-SHB-B reliable?
The price and inventory of AT25SF161B-SHB-B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25SF161B-SHB-B is usually 5 days.
3.What payment methods are accepted for AT25SF161B-SHB-B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25SF161B-SHB-B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25SF161B-SHB-B?
AT25SF161B-SHB-B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25SF161B-SHB-B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25SF161B-SHB-B?
For technical support, including AT25SF161B-SHB-B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25SF161B-SHB-B requirements.
6.How does Aetrix verify that AT25SF161B-SHB-B is sourced from the original manufacturer or authorized distributors?
All AT25SF161B-SHB-B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25SF161B-SHB-B meets industry standards.
7.What is the process for return or replacement of AT25SF161B-SHB-B?
All AT25SF161B-SHB-B units undergo pre-shipment inspection (PSI). If there is an issue with AT25SF161B-SHB-B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25SF161B-SHB-B part is unused and in its original packaging.
Return procedure for AT25SF161B-SHB-B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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